Ed Sperling of Semiconductor Engineering observes that chipmakers are increasingly relying on architectural and micro-architectural changes as the “best hope” for optimizing power and performance across markets, process nodes and price points.
“While discussion about the death of Moore’s Law predates the 1-micron process node, there is no question that it is getting harder for even the largest chipmakers to stay on that curve,” he explained.
“[There is now a] growing reliance on architectures and microarchitectures to optimize power, performance and area, rather than just adding more transistors onto a die. And they put far more pressure on architects of all types—power, chip, system and software—to replace the gains once provided by device scaling.”
According to Sperling, an equal or greater emphasis is now being placed on signal throughput to memory and I/O, including parallelization, lower power consumption and how chips will provide competitive advantages for specific market uses. This approach is markedly different than previous industry paradigms which saw companies focus on the performance specs of a single, general-purpose processor.
Commenting on the above, Steven Woo, VP of Systems and Solutions at Rambus, confirmed the semiconductor industry is no longer able to depend on dramatic performance and power efficiency gains from Moore’s Law and Dennard Scaling, which is why we are seeing a salient increase in smart data acceleration. Indeed, while smaller process geometries continue to provide more transistors per chip, clock speeds are plateauing due to power and thermal limits, with instructions per clock cycle remaining relatively static as well.
“We’ve been relying on Moore’s Law for several decades, and it’s outpaced technology improvements in storage, networking and memories,” Woo told Semiconductor Engineering. “But times have changed and there is so much more data these days. Bottlenecks have shifted and there’s a big issue with moving that data. In many cases, it’s better to move the processing to the data rather than to move the data to the processing. It’s smaller and more power efficient.”
Smart data acceleration, says Woo, can be implemented across a range of silicon, including CPUs, GPUs and FPGAs. The latter is particularly flexible, as it allows engineers to quickly test out new concepts and can be attached to the very same type of memories as CPUs. To be sure, design teams have for years started with an FPGA before committing to an ASIC. This is because reprogrammable and reconfigurable FPGAs can be loaded with a wide range of algorithms – without the high costs typically associated with ASICs.
Moreover, when paired with traditional CPUs, FPGAs are capable of providing application-specific hardware acceleration that can be updated over time. Applications can also be partitioned into parts that run most efficiently on the CPU and other segments which run most efficiently on the FPGA.
“We believe FPGAs will exist alongside other silicon and will continue to play an important role in helping evolve computing platforms by enabling flexible acceleration and near data processing,” he added.
Interested in learning more? You can check out our Smart Data Acceleration (SDA) program here.