Writing for Semiconductor Engineering, Ernest Worthman notes that while stacked die may improve performance and lower power, the use of through-silicon vias (TSVs) could potentially add new security risks. “With 2.5D architectures, IP blocks can be designed on separate dies and assembled using an interposer. Such a chip can have a stacked DRAM, a Wi-Fi radio and flash memory, together with the processor in a single package,” Worthman explained.
Are stacked die creating new security risks?
Rambus Unveils On-chip Noise Monitor to Improve Quality and Reduce Time-to-Market of Complex SoCs
Compact IP enables accurate characterization of power supply noise in mobile and server applications
SUNNYVALE, Calif. – January 20, 2015 – Rambus Inc. (NASDAQ:RMBS) today announced the addition of an On-chip Noise Monitor to its suite of tools and IP cores. The Noise Monitor is a compact IP block that enables easy and precise noise measurements for both low-power mobile and high-performance server SoCs. Embedded on-chip, the noise monitor eliminates the need to use slow and often error-prone hand-probing techniques, improving the quality of silicon test results and speeding time-to-market.
“As the system requirements for smartphones, tablets and servers continue to drive higher data rates and reduced power, designers are facing increasingly difficult challenges to accurately measure and characterize SoC power supply noise,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “The fast and accurate results delivered by the On-chip Noise Monitor provide designers a better understanding of the affects of noise and circuit performance and an increased confidence in the quality of IC design.”
The Noise Monitor is an extremely small IP block that is integrated directly into the complex IC capable of measuring noise at frequencies as high a 6 gigahertz (GHz). This makes it ideal for high data rate applications, as well as those that use package-on-package and 2.5/3D packaging. When coupled with the Rambus LabStation™ Validation Platform, designers are able to precisely measure multiple aspects of power supply noise using only the LabStation Interface Module (LIM) and a personal computer.
Rambus will be demonstrating the On-chip Noise Monitor along with its R+™ enhanced standard memory and serial link cores at the upcoming DesignCon 2015 conference in booth 835, January 28-29, 2015.
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About Rambus Inc.
Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.
On-chip Noise Monitor accelerates time-to-market for complex SOCs
Rambus has added an On-chip Noise Monitor to its suite of tools and IP cores. According to Loren Shalinsky, a Strategic Development Director at Rambus, the Noise Monitor is designed to accurately characterize power supply noise of low- power, high-performance complex IPs and electronic systems.
Xiaomi’s Mi Note Pro is loaded with 4GB of RAM
Announced earlier this month at CES 2015, the Asus Zenfone 2 features a 64-bit Intel Atom Z3580 processor and supports up to 4GB LPDDR3 DRAM. As we previously confirmed on Rambus Press, the Zenfone 2 was the very first smartphone to carry a full payload of 4GB of RAM. Unsurprisingly, a number of manufacturers are eyeing 4GB of RAM for their next-gen smartphones and phablets.
DSI Demo (Northwest Logic, Mixel)
Demonstration of Northwest Logic’s DSI Controller Core with Mixel’s D-PHY.
To learn more about the Rambus DSI-2 Controller Core, click here.
CSI – DVI Demo (Northwest Logic, Mixel)
Demonstration of Rambus’, formerly Northwest Logic, CSI-2 Controller Core with Mixel’s D-PHY.
To learn more about the Rambus CSI-2 Controller Core, click here.
