At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 221 Results
PCIe 3.1 Controller
https://www.rambus.com/interface-ip/pci-express/pcie3-controller/PCIe 3.1 Controller Contact Us The PCIe 3.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. A PCIe 3.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity […]
Debug and Test Solutions
https://www.rambus.com/interface-ip/pci-express/debug-and-test-solutions/Debug and Test Solutions Contact Us INSPECTOR for PCIe 5.0 Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to Gen5 32 GT/s speed. ContactProduct Brief Inspector for PCIe 5.0 INSPECTOR is a PCIe 5.0-compliant interposer module designed for non-intrusive monitoring, diagnostic, exercising and debug of PCIe devices. INSPECTOR uses transparent switching […]
CXL 2.0 Controller
https://www.rambus.com/interface-ip/cxl/cxl2-controller/CXL 2.0 Controller Contact Us Rambus Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface […]
Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem
https://www.rambus.com/rambus-advances-ai-ml-performance-with-hbm3-ready-memory-subsystem/Highlights: Provides HBM3-ready memory subsystem solution consisting of fully-integrated PHY and digital controller Supports data rates up to 8.4 Gigabits per second (Gbps), enabling terabyte-scale bandwidth accelerators for artificial intelligence/machine learning (AI/ML) and high-performance computing (HPC) applications Leverages market-leading HBM2/2E experience and installed-base to speed implementation of customer designs using next-generation HBM3 memory SAN JOSE, […]
Rambus to Acquire PLDA, Extending Leadership with Cutting-Edge CXL™ and PCI Express® Digital IP
https://www.rambus.com/rambus-to-acquire-plda/Expands digital controller IP portfolio with complementary CXL 2.0, PCIe® 5.0 and PCIe 6.0 controller and switch IP Enables integrated interface subsystem solutions for data center, artificial intelligence and machine learning (AI/ML), and High Performance Computing (HPC) Provides critical building blocks for Rambus CXL Memory Interconnect Initiative to advance high-bandwidth connectivity SAN JOSE, Calif. – June […]
Rambus to Acquire AnalogX, Accelerating Next-Generation Data Center Interface Solutions
https://www.rambus.com/rambus-to-acquire-analogx/Extends leadership in PCIe® 5.0 and 32G Multi-protocol SerDes with ultra-low power interface IP Accelerates time to market and enhances the Rambus roadmap for PAM4-based PCIe 6.0 and CXL™ 3.0 solutions for data center, artificial intelligence and machine learning (AI/ML), 5G and High Performance Computing (HPC) Provides critical building blocks for Rambus CXL Memory Interconnect […]
New interface architectures enable data scaling
https://www.rambus.com/blogs/new-interface-architectures-enable-data-scaling/Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes a closer look at why data center scaling requires new interface architectures. As Andani notes, global data traffic is growing at an exponential rate. More specifically, 5G networks are enabling billions of AI-powered IoT devices untethered from […]
Designing chiplet and co-packaged optics architectures with 112G XSR SerDes
https://www.rambus.com/blogs/designing-chiplet-and-co-packaged-optics-architectures-with-112g-xsr-serdes/Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes an in-depth look at how 112G XSR SerDes can be used to optimally design chiplet and co-packaged optics architectures. As Andani notes, conventional chip designs are struggling to achieve the scalability, as well as power, performance, and […]
Powering the Next Wave of AI Applications
https://www.rambus.com/blogs/powering-the-next-wave-of-ai-applications/Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training models has passed 100 billion parameters and is on pace to hit a trillion in the next year. The impact of AI/ML is being felt across the industry landscape, in higher education, and in financial markets. Underpinning this growth is […]
Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14/11nm
https://www.rambus.com/rambus-expands-high-performance-memory-subsystem-offerings-with-hbm2e-solution-on-samsung-14-11nm/Highlights: Supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14/11nm FinFET process Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market SAN JOSE, Calif. – April 21, 2021 – Rambus […]
