Suresh Andani, senior director of product marketing at Rambus, has written an article for Semiconductor Engineering that takes an in-depth look at how 112G XSR SerDes can be used to optimally design chiplet and co-packaged optics architectures.
As Andani notes, conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA) that are expected of leading-edge designs.
“With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is [also] a growing challenge,” he explains. “In this context, disaggregated architectures such as chiplets or co-packaged optics (CPO) become truly viable alternatives to the traditional monolithic SoC scaling approach.”
According to Andani, aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields.
“This is precisely why chiplets are already enabling a wide range of applications across multiple mainstream markets such as the data center, networking, 5G, high-performance computing (HPC), and artificial intelligence/machine learning (AI/ML),” he elaborates. “It also allows different process technologies to be mixed and matched with functions implemented in the most appropriate node.”
As Andani observes, a similar rationale exists for CPO, with next-generation 51.2 Terabit per second (Tbps) switch ASICs slated to be co-packaged with sixty-four (64) 800G silicon photonics die.
“Trying to integrate both logic and the silicon photonics required for the needed bandwidth in a single chip would be completely impractical,” he states. “Conversely, very short reach electrical links interconnecting a packaged 51.2T ASIC with separately packaged optical modules would burn too much power.”
The solution, says Andani, is co-packaging ASIC and optics connected with ultra-low power, extra short reach (XSR) SerDes links. This disaggregated architecture allows for logic and optics to be implemented in the best-fit process nodes for each, reduces complexity and achieves power targets.
For AI/ML and HPC SoCs, the 112G XSR SerDes is used to bridge purpose-built accelerator chiplets for natural language processing, video transcoding, and image recognition. Another popular use case, says Andani, is the die disaggregation of large SoCs (which are hitting reticle size limits for manufacturable yields) into multiple smaller die that are connected with XSR links over organic substrate.
“As the semiconductor industry turns towards chiplets and CPO to enable high-performance products, implementation of the SerDes PHY is critical to effectively maintain high speeds and signal integrity across XSR and ultra-short reach (USR) distances,” he explains. “From our perspective, 112G XSR SerDes PHYs fabricated in advanced process nodes – such as 7nm – can successfully deliver the required speed and signal integrity demanded by chiplets and co-packaged optics. The 112G XSR interface – formalized by the Optical Internetworking Forum (OIF) – offers extremely high throughput capabilities, even though it is designed for low complexity and very low power consumption.”
As Andani points out, 112G XSR SerDes PHYs should be tailored for the ultra-low power and area requirements of die-to-die (D2D) and die-to-optical-engine (D2OE) interfaces, supporting NRZ and PAM-4 signaling at multiple data rates for maximum design flexibility.
Additional features should optimally include a high-bandwidth ~2Tbps/mm of uni-directional beachfront efficiency, support for channels up to 10dB insertion loss without DFE (to save power), multiple lane configurations to allow flexible ASIC floorplan integration, extensive Design-For-Test (DFT) capabilities to aid manufacturing of Known Good Dice (KGD), static and run-time debug capabilities, and software and scripts for enhanced bring-up and validation.
“In a world of Moore’s Law slowing and Dennard Scaling stopped, the traditional approach of implementing monolithic SoCs faces real challenges,” he adds. “Complexity, yield, and power consumption become insurmountable obstacles to delivering the PPA required by leading-edge applications.”
Fortunately, disaggregated architectures, namely chiplets and CPO, break through these limits. High-speed, extra and ultra-short reach links delivered by 112G XSR SerDes PHYs are the key technology for interconnecting chiplets, ASICs and optics.
“With 112G XSR SerDes, chiplets and CPO will enable the most demanding applications across the data center, networking, 5G, HPC, and AI/ML markets,” Andani concludes.