At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 90 Results
CXL Memory Initiative
https://www.rambus.com/cxl-memory-initiative/CXL Memory Initiative Enabling new memory tiers for breakthrough server performance Contact Us Data Center Challenges Data centers face three major memory challenges as roadblocks to greater performance and total cost of ownership (TCO). Data Center Memory Challenges The first of these is the limitations of the current server memory hierarchy. There is a three […]
Avery Design Systems and Rambus Extend Memory Model and PCIe® VIP Collaboration
https://www.rambus.com/avery-design-systems-and-rambus-extend-memory-model-and-pcie-vip-collaboration/Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory […]
Stacking memory for AI/ML training with HBM2E
https://www.rambus.com/blogs/stacking-memory-for-ai-ml-training-with-hbm2e/Frank Ferro, Senior Director Product Management at Rambus, recently penned an article for Semiconductor Engineering that takes a closer look at high bandwidth memory (HBM) and 2.5D (stacking) architecture for AI/ML training. As Ferro notes, the impact of AI/ML increases daily – impacting nearly every industry across the globe. “In marketing, healthcare, retail, transportation, manufacturing […]
Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14/11nm
https://www.rambus.com/rambus-expands-high-performance-memory-subsystem-offerings-with-hbm2e-solution-on-samsung-14-11nm/Highlights: Supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14/11nm FinFET process Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market SAN JOSE, Calif. – April 21, 2021 – Rambus […]
Rambus Joins DARPA Toolbox Initiative with State-of-the-Art Security and Interface IP
https://www.rambus.com/rambus-joins-darpa-toolbox-initiative-with-state-of-the-art-security-and-interface-ip/Highlights: Agreement makes Rambus Root of Trust, Secure Protocol Engines, along with Memory and SerDes PHYs and Controllers available to DARPA researchers Streamlined access to cutting-edge silicon IP accelerates forward-looking innovation DARPA researchers will be able to leverage industry-leading capabilities and expertise from Rambus SAN JOSE, Calif. – April 14, 2021 – Rambus Inc. (NASDAQ: RMBS), a provider of […]
HBM2E targets AI/ML training
https://www.rambus.com/blogs/hbm2e-targets-ai-ml-training/Frank Ferro, Senior Director Product Management at Rambus, has written a detailed article for Semiconductor Engineering that explains why HBM2E is a perfect fit for Artificial Intelligence/Machine Learning (AI/ML) training. As Ferro points out, AI/ML growth and development are proceeding at a lighting pace. Indeed, AI training capabilities have jumped by a factor of 300,000 […]
MACsec Explained: Securing Data in Motion
https://www.rambus.com/blogs/macsec/Learn everything you need to know about MACsec, also known as Media Access Control Security. For end-to-end security of data, it needs to be secured when at rest (processed or stored in a device) and when in motion (communicated between connected devices). For data at rest, a hardware root of trust anchored in silicon provides […]
The Ultimate Guide to HBM2E Implementation & Selection
https://www.rambus.com/blogs/hbm2e/This is the most comprehensive guide to selecting and implementing a HBM2E memory IP interface solution. Frank Ferro and Joseph Rodriguez, Senior Directors Product Management at Rambus, hosted a webinar at our Rambus Design Summit discussing HBM2 and HBM2E memory technology. There’s a lot of decisions that need to be made when you’re developing high […]
AI Requires Tailored DRAM Solutions: Part 4
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-4/Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part three of this four-part series touched on a wide range of topics including the impact of AI on specific hardware systems, training […]
Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
https://www.rambus.com/rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications/Highlights: Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry’s fastest performance New benchmark in performance supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS® advanced packaging technologies Offers unrivaled […]
