At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 142 Results
High-Performance Memory for AI/ML and HPC: Part 1
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
Rambus Reports First Quarter 2020 Financial Results
https://www.rambus.com/first-quarter-2020-financial-results/Excellent quarter, exceeding expectations for revenue and profit: GAAP revenue of $64.0 million; licensing billings of $67.1 million, product revenue of $30.7 million, and contract and other revenue of $13.6 million $37.3 million in cash provided by operating activities, further strengthening the balance sheet Record revenue from both the silicon IP and chip businesses, bolstered […]
Memory a Key Enabler of Continued Advancement of AI/ML
https://www.rambus.com/blogs/memory-a-key-enabler-of-continued-advancement-of-ai-ml/Recently Rambus fellow and distinguished inventor, Steve Woo, had a web chat with Bill Wong, technology editor for Electronic Design, to discuss some of the latest hardware trends in AI/ML. This was part of an ongoing conversation Steve and Bill have had regarding leading-edge developments in the AI/ML revolution. In the webcast, Steve discusses some […]
Memory Systems for AI: Part 6
https://www.rambus.com/blogs/memory-systems-for-ai-part-6/Written by Steven Woo for Rambus Press In part 5 of this series, we discussed the most common memory systems that are used in the highest performance AI applications. These include on-chip memory, high bandwidth memory (HBM) and Graphics DDR SDRAM (GDDR SDRAM). In this blog post, we’ll take an in-depth look at on-chip memory, […]
2.5D/3D Packaging Solutions for AI and HPC (Chinese)
https://go.rambus.com/packaging-solutions-for-ai-and-hpc-chinese#new_tabFor AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.
Memory Systems for AI: Part 4
https://www.rambus.com/blogs/memory-systems-for-ai-part-4/Written by Steven Woo for Rambus Press In part three of this series, we discussed how a Roofline model can help system designers better understand if the performance of applications running on specific processors is limited more by compute resources, or by memory bandwidth. Rooflines are particularly useful when analyzing machine learning applications like neural […]
Rambus’ HBM2E Memory Controller & PHY Offer Chipmakers Cost-Effective Designs
https://www.tomshardware.com/news/rambus-hbm2e-memory-controller-phy-designs#new_tabThe latest generation of high-bandwidth memory, HBM2E, is around the corner. Now that Samsung has started mass production of its HBM2E memory stacks, Rambus has unveiled its controller and PHY (physical interface) designs.
Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus
https://www.anandtech.com/show/15599/rambus-develops-hbm2e-controller-phy-32-gbps-1024bit-bus#new_tabThe latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so […]
Memory Systems for AI: Part 3
https://www.rambus.com/blogs/memory-systems-for-ai-part-3/Written by Steven Woo for Rambus Press In part two of this series, we took a closer look at how the upcoming deployment of 5G technology will enable processing at the edge, and how the industry is further refining the edge into the near edge and the far edge. The near edge is closer to […]
Complete Memory Interface Solution for HBM2E Launched
https://www.rambus.com/blogs/complete-memory-interface-solution-for-hbm2e-launched/Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack. Read first our primer on: HBM2E Implementation & Selection – The […]
