At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 140 Results
Rambus Reports Third Quarter 2019 Financial Results
https://www.rambus.com/third-quarter-2019-financial-results/Great quarter, exceeding expectations; GAAP revenue of $57.4 million; licensing billings of $63.1 million, product revenue of $21.4 million, and contract and other revenue of $16.6 million $25.6 million in cash provided by operating activities Refocused business on semiconductor with completed sale of payments and ticketing business to Visa Expanded silicon IP offerings with acquisition […]
Chiplets keep the scaling of integrated circuits (ICs) rolling
https://www.rambus.com/blogs/chiplets-keep-the-scaling-of-integrated-circuits-ics-rolling/As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when our old friend Moore’s Law has lost a step. However, as the complexity of SOCs increases, so […]
Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process
https://www.rambus.com/rambus-announces-portfolio-of-advanced-memory-and-serdes-phys-on-tsmc-n7-process/Highlights: GDDR6, HBM2, and 112G Long Reach (LR) interfaces designed for TSMC’s industry-leading N7 process technology expand Rambus’ leading-edge memory and SerDes PHY offerings Portfolio enables critical building blocks for next-generation data center, networking, wireless 5G, high-performance computing (HPC), advanced driver assistance systems (ADAS), artificial intelligence (AI) and machine learning (ML) applications SUNNYVALE, Calif. and […]
HBM2 or GDDR6?
https://www.rambus.com/blogs/hbm2-or-gddr6/Earlier this month, Semiconductor Engineering editor-in-chief Ed Sperling hosted an industry roundtable to discuss new DRAM options and considerations. Frank Ferro, our senior director of product management, represented Rambus, alongside participants from Cadence, Synopsys and Samsung Electronics. Read first our primer on: HBM2E Implementation & Selection – The Ultimate Guide » As Ferro points out, […]
Part 2: Steven Woo Explains GDDR6 – HBM2 Design Tradeoffs
https://www.rambus.com/blogs/part-2-steven-woo-explains-gddr6-hbm2-design-tradeoffs/In part one of this two-part series, Steven Woo, Rambus fellow and distinguished inventor, speaks with Ed Sperling of Semiconductor Engineering about the basic design tradeoffs between GDDR6 and HBM2. To illustrate the differences between the two memory types, Woo highlights a 256 gigabyte per second memory system built using either GDDR6 or HBM2. In […]
Rambus Completes Acquisition of Northwest Logic, Extending Leadership in Interface IP
https://www.rambus.com/rambus-completes-acquisition-of-northwest-logic-extending-leadership-in-interface-ip/Highlights: Digital controller IP complements existing portfolio of high-speed interface PHYs Expands solutions for automotive, data center, artificial intelligence (AI), machine learning (ML) and communications applications Combined offerings, including HBM2, GDDR6, DDR4 and PCI Express (PCIe), create one-stop-shop for SoC designers SUNNYVALE, Calif. – Aug. 27, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon […]
Rambus Completes Acquisition of Northwest Logic, Extending Leadership in Interface IP
https://www.rambus.com/rambus-completes-acquisition-of-northwest-logic/Highlights: Digital controller IP complements existing portfolio of high-speed interface PHYs Expands solutions for automotive, data center, artificial intelligence (AI), machine learning (ML) and communications applications Combined offerings, including HBM2, GDDR6, DDR4 and PCI Express (PCIe), create one-stop-shop for SoC designers SUNNYVALE, Calif. – Aug. 27, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon […]
Part 1: Steven Woo Explains GDDR6 – HBM2 Design Tradeoffs
https://www.rambus.com/blogs/part-1-steven-woo-explains-gddr6-hbm2-design-tradeoffs/Steven Woo, Rambus fellow and distinguished inventor, recently spoke with Ed Sperling of Semiconductor Engineering about designing systems with GDDR6 and HBM2. As Woo emphasizes, understanding engineering tradeoffs are an important part of deciding how to best match a system with the most appropriate memory. Read first our primer on: HBM2E Implementation & Selection – […]
The HPC Bottlenecks of Amdahl’s Other Law
https://www.rambus.com/blogs/the-hpc-bottlenecks-of-amdahls-other-law/Written by Steven Woo As we discussed in our previous blog post, there is a sense of growing concern in the high-performance computing (HPC) space over successive generations of supercomputers that have continued to move further and further away from architectural balance between compute and memory resources. This is because compute performance has improved at […]
Reassessing the HPC Memory Hierarchy
https://www.rambus.com/blogs/reassessing-the-hpc-memory-hierarchy/Written by Steven Woo As we’ve discussed in previous Rambus blog posts, high-performance computing (HPC) memory bandwidth and capacity are continuing to fall further and further behind the performance of compute engines. Consequently, memory and I/O subsystems are becoming increasingly larger bottlenecks that must be carefully managed by applications and operating systems. There is also […]
