At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 212 Results
AI Requires Tailored DRAM Solutions: Part 2
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-2/Written by Rambus Press Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part one of this four-part series reviewed a range of topics including the interconnected system landscape, the impact of […]
Rambus Demonstrates HBM2E Running at 4 Gbps: 512 GB/s per HBM2E Stack
https://www.tomshardware.com/news/rambus-demonstrates-hbm2e-running-at-4-gbps-512-gbs-per-hbm2e-stack#new_tabRambus has demonstrated that its HBM2E solution, which consists of a memory controller and a verified 1024-bit PHY, can operate at a whopping 4.0 Gbps data transfer rate per pin. The demonstration is meant to prove potential clients that the HBM2E solution can scale and offer a 25% higher peak bandwidth than is officially defined by JEDEC’s […]
Rambus Announces 2020 Design Summit
https://www.rambus.com/blogs/rambus-announces-2020-design-summit/The Rambus 2020 Design Summit kicks off on Thursday, October 08, 2020 at 09:00 AM Pacific Daylight Time. Throughout the day, our technology experts will discuss the selection and implementation of IP solutions across multiple markets such as the data center, 5G/edge and IoT devices, and AI/ML applications. Critical enabling IP that will be covered […]
Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
https://www.rambus.com/rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications/Highlights: Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry’s fastest performance New benchmark in performance supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS® advanced packaging technologies Offers unrivaled […]
Rambus Design Summit
https://www.rambus.com/rambus-design-summit-2/October 8, 2020 Register Today Join us for a day of virtual sessions covering the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices including advancing the performance of AI/ML applications. Connect with a community of industry experts and gain insights and practical information for the implementation of their next-generation […]
High-Performance Memory for AI/ML and HPC: Part 2
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-2/In part one of this two-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Rambus Sr. Director of Product Management Frank Ferro took a closer look at the various types of memory that system designers are using to support artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. In this blog post, […]
High-Performance Memory for AI/ML and HPC: Part 1
https://www.rambus.com/blogs/high-performance-memory-for-ai-ml-and-hpc-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
Rambus Reports First Quarter 2020 Financial Results
https://www.rambus.com/first-quarter-2020-financial-results/Excellent quarter, exceeding expectations for revenue and profit: GAAP revenue of $64.0 million; licensing billings of $67.1 million, product revenue of $30.7 million, and contract and other revenue of $13.6 million $37.3 million in cash provided by operating activities, further strengthening the balance sheet Record revenue from both the silicon IP and chip businesses, bolstered […]
The Thermal Challenges of Moore’s Law: Part 2
https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-2/In part one of this two-part blog series, Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law and the thermal challenges faced by the semiconductor industry. Specifically, Woo highlighted how the breakdown of Dennard scaling around 2005 prompted GPU designers to place […]
Memory a Key Enabler of Continued Advancement of AI/ML
https://www.rambus.com/blogs/memory-a-key-enabler-of-continued-advancement-of-ai-ml/Recently Rambus fellow and distinguished inventor, Steve Woo, had a web chat with Bill Wong, technology editor for Electronic Design, to discuss some of the latest hardware trends in AI/ML. This was part of an ongoing conversation Steve and Bill have had regarding leading-edge developments in the AI/ML revolution. In the webcast, Steve discusses some […]
