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Compute Express Link (CXL): All you need to know

Last updated on: December 19, 2022 In this blog post, we take an in-depth look at Compute Express Link ™ (CXL™), an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) […]

AI Hardware Summit Event Recap: Interview with Steven Woo

The fifth annual AI Hardware Summit was back this month, and for the first time in a couple of years, it took place fully in-person in Santa Clara, California. The world’s leading experts in AI hardware came together over the course of three days to discuss some of the big challenges facing the industry, and […]

FIPS Crypto Library

Security FIPS Crypto Library The Rambus FIPS Crypto Library is a modern cryptographic library which offers up-to-date implementations of all major cryptographic algorithms and primitives. The FIPS Crypto Library contains a FIPS validated crypto module, a standard crypto library for non FIPS algorithms and a crypto API for easy use and integration. The FIPS Crypto […]

Rambus Design Summit Interview Series: Steven Woo

Rambus Fellow, Steven Woo, returns to the Rambus Design Summit stage tomorrow, and we are so excited for his keynote: Advancing Computing in the Accelerator Age! In our last interview before the show, we met with Steven to chat about his background, CXL, and some of the biggest challenges for computing in the years ahead. Read […]


Security 1G to 50G Single-Port MACsec Engine with xMII interface and TSN support The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example DMA-MAC Ethernet controllers or switch core IP […]

PCIe 6.0 Retimer Controller with CXL Support

Interface IP PCIe 6.0 Retimer Controller with CXL Support PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on standard PCBs. Extending trace routing beyond this distance results in higher first bit error rates (FBER) and reduced link efficiency due to […]

Video Compression and Forward Error Correction Cores

Interface IP Video Compression and Forward Error Correction Cores Rambus visually lossless video compression and FEC IP cores (formerly from Hardent) enable designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. We offer a range of high-quality solutions designed to support the latest video […]

Autonomous Vehicles: Everything about self-driving cars explained

A self-driving car is a computer-controlled vehicle that drives itself. Also referred to as an autonomous vehicle, driverless car, or robotic car (robo-car), a self-driving car analyzes its environment to safely move and react without human input. In this article, you’ll learn: 6 levels of autonomous cars History of autonomous vehicles How do self-driving cars […]

Inline Memory Encryption Engine

Security IME-IP-340 Inline Memory Encryption Engine IME-IP-340 Inline Memory Encryption (IME) Engine provides just-in-time encryption, decryption and authentication for all memory read and write requests between a host processor and its attached memory. Absent encryption, instruction and data stored in external memory are vulnerable to attack, introspection, or modification as they are loaded and executed. […]

IME-IP-339 Inline Memory Encryption Engine

Security ICE-IP-339 Inline Cipher Engine with AXI Modern computing architectures must address increasing concerns regarding off-chip data confidentiality. Key drivers for these concerns are data privacy for attacks with physical access to memory, confidential computing using zero trust computing architectures, regulatory frameworks, and secure encrypted resource virtualization e.g., multi-tenancy support among others. Inline memory encryption […]