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Third quarter GAAP revenue of $59.8 million; revenue under ASC 605 would have been $99.8 million, in line with expectations; $31.6 million in cash provided by operating activities Third quarter GAAP royalty revenue of $33.6 million, royalty revenue under ASC 605 would have been $75.7 million and licensing billings of $75.4 million New and renewed […]
The single software ecosystem built on the RISC-V standard allows for OEMs to bypass having to lock into a specific processer ecosystem. When an OEM chooses a particular processor type, it not only has to pay for that particular processor, but it has to continue to purchase from whichever company it purchased it processor from, leading to a market where profits are not driven by competition
Reduced Instruction Set Computing Five (RISC-V) is an open Instruction Set Architecture (ISA) designed with small, fast, and low-power real-world implementations in mind. It describes the way in which software talks to an underlying processor
Second quarter GAAP revenue of $56.5 million; revenue under ASC 605 would have been $98.8 million, in line with expectations Second quarter GAAP royalty revenue of $30.1 million, royalty revenue under ASC 605 would have been $73.6 million and licensing billings of $73.2 million Record number of licensing deals closed in Q2, including IBM and […]
Mike Noonen Joins Rambus to Grow RISC-V and Memory Ecosystems SUNNYVALE, Calif. – May 29, 2018 – Rambus Inc. (NASDAQ: RMBS) today announced the appointment of Mike Noonen as senior vice president of global market development. Mr. Noonen will expand the Rambus semiconductor and memory ecosystem and will report to president and chief executive officer, […]
First quarter GAAP revenue of $46.4 million; revenue under ASC 605 would have been $100.5 million First quarter GAAP royalty revenue of $21.4 million, royalty revenue under ASC 605 would have been $77.2 million and licensing billings of $75.9 million Record revenue for Memory and Interface IP Cores Launched CryptoManager Root-of-trust programmable secure processing core […]
Taking a closer look: The Rambus CMRT The recent Meltdown and Spectre vulnerabilities illustrate the critical need for a new generation of devices that execute sensitive security functions in a secure core which is physically separated from the primary CPU. This is precisely why Rambus is launching its CryptoManager Root of Trust, a fully programmable hardware […]
Mitigates security vulnerabilities like Meltdown and Spectre SUNNYVALE, Calif., and SAN FRANCISCO – April 16, 2018 – Rambus Inc. (NASDAQ: RMBS) today announced the availability of the CryptoManager Root of Trust, a fully programmable hardware security core built with a custom RISC-V CPU. The secure processing core creates a siloed architecture that isolates and secures the execution of […]
Next-gen Rambus RISC-V security products Last week, we confirmed the selection of Codasip Studio for the development of our next-generation RISC-V security products. According to Bret Sewell, SVP and general manager of the Rambus Security Division, Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. More specifically, Codasip Studio […]
Revenue of $99.1 million, up 10% year over year GAAP diluted net income per share of $0.07; non-GAAP diluted net income per share of $0.19 Announced industry’s first silicon-proven server DIMM buffer chipset capable of achieving the speeds expected for next-generation DDR5 Teamed up with eftpos domestic debit card network in Australia to support roll […]