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This document describes requirements and test procedures for qualifying DPA-resistant implementations of cryptographic algorithms with specific instructions and test vectors for AES. Expected lab and analyst proficiency, device setup, data acquisition, signal processing, analysis and evaluation procedures are described herein. Download “Test Vector Leakage Assessment (TVLA) Derived Test Requirements (DTR) with AES”
Ecosystem Partners Universities and Research Institutes Rambus collaborates with a range of world-class academic institutions and research-based organizations to drive the development and improvement of key intellectual property. Contact Universities & Organizations:
Ecosystem Partners SSOs & Consortiums Rambus is actively engaged with a number of organizations and consortiums that develop standards to drive adoption of memory, interface, and semiconductor security technology and solutions. Contact The CXL Consortium is an open industry standard group formed to develop technical specifications that facilitate breakthrough performance for emerging usage models while […]
Ecosystem Partners Industry Alliances Rambus has developed alliances with industry partners and academic institutions to develop and implement best-in-class memory, interface, and semiconductor security solutions Contact The Aerospace Industries Association (AIA) is the voice of the U.S. aerospace and defense industry, establishing industry-wide goals and strategies to provide solutions to issues that impact members and […]
Ecosystem Partners Rambus Partner Program Rambus collaborates with industry-leading companies to create an ecosystem that provides total solutions for our customers. Ecosystem partners include semiconductor foundries, physical (PHY) IP developers, microprocessor IP vendors, FPGA suppliers, EDA tools and validation labs, ASIC and SoC designers, and DPA solution providers. Semiconductor Foundries Most Rambus IP solutions are […]
Our Binary Pixel technology combines a breakthrough imager and processing architecture to enable professional quality images from mobile phones and point-and-shoot consumer cameras. The technology mimics the brilliance of human visual processing by sensing photons using discrete thresholds similar to the rods and cones of the human eye. This “binary operation” allows the imager to […]
Reduced power consumption has become of key importance in memory system design—from mobile to enterprise-class applications. In addition to clocking power and DRAM core access power, IO signaling power must be addressed in order to reduce the total power consumption of the memory system. Near ground signaling is a single-ended, ground-terminated technology theat enables high […]
The growing trend of multi-core processing and converged graphics-compute processors is increasing the performance requirements on the DRAM memory subsystems. Multi-thread computing and graphics not only need higher memory bandwidth but also generate more random accesses to smaller pieces of data. Module Threading improves the throughput and power efficiency of a memory module by applying […]
Precise on-chip alignment of data clock are crucial for today’s high performance memory systems. In addition, offsets in timing caused by variations in process, voltage and timing must be accounted for. FlexPhase™ Timing Adjustment Circuits are a key technology ingredient for achieving high data rates on chip-to-chip systems that reference an external clock signal. By […]
Many electronic devices that use cryptography are susceptible to side channel attacks. These low-cost, non-invasive methods enable attackers to extract the secret cryptographic keys used during normal device operations by monitoring a device’s timing, power consumption, or electromagnetic emissions. Side channel attacks leave no trace, and can often be performed quickly using consumer-level equipment. Once […]
