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Tezzaron to Incorporate Rambus ReRAM Memory Technology
https://www.rambus.com/tezzaron-to-incorporate-rambus-reram-memory-technology/Architecture enhances power and performance in military, aerospace and commercial applications SUNNYVALE, Calif. and Naperville, Ill. – January 22, 2015 – Rambus Inc. (NASDAQ:RMBS) and Tezzaron Semiconductor today announced that they have signed an agreement to incorporate Rambus oxide-resistive memory (ReRAM) technology in forthcoming Tezzaron devices. This architecture license gives Tezzaron access to system IP, […]
Tezzaron licenses Rambus ReRAM
https://www.rambusblog.com/2015/01/22/tezzaron-licenses-rambus-reram/#new_tabRambus and Tezzaron Semiconductor have clinched an agreement to incorporate Rambus oxide-resistive memory (ReRAM) technology in upcoming Tezzaron devices. According to Rambus Labs VP Gary Bronner, the architecture license grants Tezzaron access to system IP, specifications and validation suites to design differentiated chips using ReRAM.
Tezzaron licenses Rambus ReRAM
https://www.rambus.com/blogs/tezzaron-licenses-rambus-reram-2/Rambus and Tezzaron Semiconductor have clinched an agreement to incorporate Rambus oxide-resistive memory (ReRAM) technology in upcoming Tezzaron devices. According to Rambus Labs VP Gary Bronner, the architecture license grants Tezzaron access to system IP, specifications and validation suites to design differentiated chips using ReRAM. “ReRAM is ideally suited to improve the power, performance and […]
Are stacked die creating new security risks?
https://www.rambusblog.com/2015/01/21/are-stacked-die-creating-new-security-risks/#new_tabWriting for Semiconductor Engineering, Ernest Worthman notes that while stacked die may improve performance and lower power, the use of through-silicon vias (TSVs) could potentially add new security risks. “With 2.5D architectures, IP blocks can be designed on separate dies and assembled using an interposer. Such a chip can have a stacked DRAM, a Wi-Fi […]
Are stacked die creating new security risks?
https://www.rambus.com/blogs/are-stacked-die-creating-new-security-risks-2/Writing for Semiconductor Engineering, Ernest Worthman notes that while stacked die may improve performance and lower power, the use of through-silicon vias (TSVs) could potentially add new security risks. “With 2.5D architectures, IP blocks can be designed on separate dies and assembled using an interposer. Such a chip can have a stacked DRAM, a Wi-Fi […]
Rambus Unveils On-chip Noise Monitor to Improve Quality and Reduce Time-to-Market of Complex SoCs
https://www.rambus.com/rambus-unveils-on-chip-noise-monitor/Compact IP enables accurate characterization of power supply noise in mobile and server applications SUNNYVALE, Calif. – January 20, 2015 – Rambus Inc. (NASDAQ:RMBS) today announced the addition of an On-chip Noise Monitor to its suite of tools and IP cores. The Noise Monitor is a compact IP block that enables easy and precise noise […]
On-chip Noise Monitor accelerates time-to-market for complex SOCs
https://www.rambusblog.com/2015/01/20/on-chip-noise-monitor-accelerates-time-to-market-for-complex-socs/#new_tabRambus has added an On-chip Noise Monitor to its suite of tools and IP cores. According to Loren Shalinsky, a Strategic Development Director at Rambus, the Noise Monitor is designed to accurately characterize power supply noise of low- power, high-performance complex IPs and electronic systems.
On-chip Noise Monitor accelerates time-to-market for complex SOCs
https://www.rambus.com/blogs/on-chip-noise-monitor-accelerates-time-to-market-for-complex-socs-2/Rambus has added an On-chip Noise Monitor to its suite of tools and IP cores. According to Loren Shalinsky, a Strategic Development Director at Rambus, the Noise Monitor is designed to accurately characterize power supply noise of low- power, high-performance complex IPs and electronic systems. “The compact, embedded IP block provides a better understanding of […]
Xiaomi’s Mi Note Pro is loaded with 4GB of RAM
https://www.rambusblog.com/2015/01/19/xiaomis-mi-note-pro-is-loaded-with-4gb-of-ram/#new_tabAnnounced earlier this month at CES 2015, the Asus Zenfone 2 features a 64-bit Intel Atom Z3580 processor and supports up to 4GB LPDDR3 DRAM. As we previously confirmed on Rambus Press, the Zenfone 2 was the very first smartphone to carry a full payload of 4GB of RAM. Unsurprisingly, a number of manufacturers are […]
DSI Demo (Northwest Logic, Mixel)
https://www.rambus.com/dsi-demo-northwest-logic-mixel/Demonstration of Northwest Logic’s DSI Controller Core with Mixel’s D-PHY. To learn more about the Rambus DSI-2 Controller Core, click here.
