At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
Found 3637 Results
Implementing CXL™ 2.0 Interconnect Solutions
https://www.rambus.com/implementing-cxl-2-0-interconnect-solutions/Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices.
Memory Bandwidth for AI/ML Races Higher with HBM3
https://www.rambus.com/memory-bandwidth-for-ai-ml-races-higher-with-hbm3/With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.
Advancing Computing in the Accelerator Age
https://www.rambus.com/advancing-computing-in-the-accelerator-age/Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.
CXL™ 3.0 Turns Up Scalability to 11
https://www.rambus.com/blogs/cxl-3-0-turns-up-scalability-to-11/The CXL™ Consortium (of which Rambus is a member) has now released the 3.0 specification of the Compute Express Link™ (CXL) standard. CXL 3.0 introduces compelling new features that promise to increase data center performance, scalability and TCO. CXL has evolved rapidly from its introduction in 2019. The 1.0/1.1 specification enabled prototyping of CXL solutions. […]
Rambus Appoints Desmond Lynch as Chief Financial Officer
https://www.rambus.com/rambus-appoints-desmond-lynch-as-chief-financial-officer/Brings over 20 years of finance and semiconductor experience SAN JOSE, Calif. – August 1, 2022 – Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, today announced it has appointed Mr. Desmond Lynch to the position of senior vice president and chief financial officer. Mr. Lynch will be responsible for […]
Rambus Reports Second Quarter 2022 Financial Results
https://www.rambus.com/second-quarter-2022-financial-results/Delivered Q2 revenue and earnings at the high end of guidance Achieved record quarterly product revenue driven by memory interface chips Expanded DDR5 portfolio with introduction of companion chips for server and client memory modules Generated $56.5 million in cash from operations SAN JOSE, Calif. – August 1, 2022– Rambus Inc. (NASDAQ:RMBS), a provider of […]
Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms
https://www.rambus.com/blogs/bulletproofing-pcie-based-socs-with-advanced-reliability-availability-serviceability-ras-mechanisms/1. Introduction As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc. The transition to PCIe 5.0 and 6.0 with increasing PCIe signaling speeds (32GT/s and 64GT/s) also increases the risk of errors due to constricted […]
SPD Hub Product Brief
https://go.rambus.com/spd-hub-product-brief#new_tabDownload this product to learn more about the Rambus SPD Hub with Temperature Sensor (PD5118-G1B).
DDR5 Temperature Sensor Product Brief
https://go.rambus.com/ddr5-temperature-sensor-product-brief#new_tabThe Rambus Temperature Sensor (TS) TS5110-G1B enables DDR5 Registered DIMMs (RDIMMs), Load Reduced DIMMs (LRDIMMs) and Non-Volatile memory DIMMs (NVDIMMs). Two TS are used per DIMM which along with the SPD Hub’s internal TS provide three points of thermal telemetry.
DDR5 Delivers More Bandwidth and Capacity with a Smarter DIMM
https://www.rambus.com/blogs/ddr5-delivers-more-bandwidth-and-capacity-with-a-smarter-dimm/The first wave of DDR5-based servers sport RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in previous generation high-performance servers. DDR5 memory incorporates a number of innovations, including Decision Feedback Equalization (DFE) and a new DIMM architecture, which enable that speed […]
