At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
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Rambus Demonstrates HBM2E Running at 4 Gbps: 512 GB/s per HBM2E Stack
https://www.tomshardware.com/news/rambus-demonstrates-hbm2e-running-at-4-gbps-512-gbs-per-hbm2e-stack#new_tabRambus has demonstrated that its HBM2E solution, which consists of a memory controller and a verified 1024-bit PHY, can operate at a whopping 4.0 Gbps data transfer rate per pin. The demonstration is meant to prove potential clients that the HBM2E solution can scale and offer a 25% higher peak bandwidth than is officially defined by JEDEC’s […]
AI Requires Tailored DRAM Solutions: Part 1
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-1/Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. In part one of this four-part series, Ferro and Rau discuss a wide range of topics including the interconnected system landscape, the impact […]
Rambus Announces 2020 Design Summit
https://www.rambus.com/blogs/rambus-announces-2020-design-summit/The Rambus 2020 Design Summit kicks off on Thursday, October 08, 2020 at 09:00 AM Pacific Daylight Time. Throughout the day, our technology experts will discuss the selection and implementation of IP solutions across multiple markets such as the data center, 5G/edge and IoT devices, and AI/ML applications. Critical enabling IP that will be covered […]
Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
https://www.rambus.com/rambus-advances-hbm2e-performance-to-4-0-gbps-for-ai-ml-training-applications/Highlights: Fully-integrated HBM2E memory interface solution, consisting of verified PHY and controller, achieves industry’s fastest performance New benchmark in performance supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Partners with SK hynix and Alchip to develop 2.5D HBM2E memory system solution using TSMC N7 process and CoWoS® advanced packaging technologies Offers unrivaled […]
Micron Reveals GDDR6X Details: The Future of Memory, or a Proprietary DRAM?
https://www.tomshardware.com/news/micron-reveals-gddr6x-details-the-future-of-memory-or-a-proprietary-dram#new_tabMicron Technology shared some additional details about its latest GDDR6X SGRAM used by Nvidia’s GeForce RTX 30-series graphics cards at a virtual briefing last week. The company revealed that it has experimented for more than a decade with technologies enabling the new type of memory and said that GDDR6X SGRAM had not been standardized by JEDEC yet. […]
Rambus Design Summit
https://www.rambus.com/rambus-design-summit-2/October 8, 2020 Register Today Join us for a day of virtual sessions covering the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices including advancing the performance of AI/ML applications. Connect with a community of industry experts and gain insights and practical information for the implementation of their next-generation […]
Rambus and Micron Extend Patent License Agreement
https://www.rambus.com/rambus-and-micron-extend-patent-license-agreement/SAN JOSE, Calif. – Sept 3, 2020 – Rambus Inc. (Nasdaq: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has extended its patent license agreement with Micron for an additional four years. The extension maintains the existing financial terms of the agreement and provides Micron with a […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 3
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-3/In part two of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed early market adoption of PCIe 5, as well as the networking environment the specification will support in the data center. In this blog post, Sperling and Andani explore […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 2
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-2/In part one of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed the evolving PCIe specification. In this blog post, Sperling and Andani explore early market adoption of PCIe 5, as well as the networking environment the specification will support […]
Micron Spills on GDDR6X: PAM4 Signaling For Higher Rates, Coming to NVIDIA’s RTX 3090
https://www.anandtech.com/show/15978/micron-spills-on-gddr6x-pam4-signaling-for-higher-rates-coming-to-nvidias-rtx-3090#new_tabIt would seem that Micron this morning has accidentally spilled the beans on the future of graphics card memory technologies – and outed one of NVIDIA’s next-generation RTX video cards in the process. In a technical brief that was posted to their website, dubbed “The Demand for Ultra-Bandwidth Solutions”, Micron detailed their portfolio of high-bandwidth […]
