Scott Best, Senior Director of Anti-Tamper Technology at Rambus, discusses the security challenges associated with AI chips and their growing deployment at the edge. Best highlights the similarities between AI chips and FPGAs, particularly in their vulnerability to attacks on valuable firmware assets, such as neural net models and RTL. He explores the importance of securing firmware from tampering and theft, emphasizing the need for encryption and authenticity verification. Best also delves into the rising threats posed by side-channel attacks like Differential Power Analysis (DPA) and offers novel solutions such as key hash chaining to protect firmware while maintaining boot efficiency. He concludes by discussing emerging risks, including neural net model extraction, and suggests tailored countermeasures to safeguard AI architectures from these attacks.
Search Results for: DPA countermeasures
AES-IP-3X SCA Resistant AES Accelerator Family
AES-IP-3X SCA Resistant AES Accelerator Family
The Rambus SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher acceleration. The cores are easily integrated into ASIC/SoC and FPGA devices and offer a high-level of resistance to various Side Channel Attacks like Differential Power Analysis (DPA), and optionally offer detection of Fault Injection Attacks (FIA).
Contact
Product BriefHow the AES-IP-3X Family works
The SCA-resistant AES-IP-3X cores perform AES encryption with SCA countermeasures using only 1 clock cycle (or 2 or 8 clock cycles for smaller configurations) per AES round, outperforming any existing solution. The cores support SCA- and FIA-resistant AES encryption and decryption in any AES mode, with 128-, 192- or 256-bit keys. The AES-IP cores implement so called double-size wide-bus interfaces (to carry two DPA shares for each protected input and output bus) and include key input, entropy data input, IV input, cipher data input, and cipher data output buses.
The unique AES cores implement highly-efficient digital SPA, DPA, CPA, DEMA, CEMA and perform at 1, 2 or 8 cycles per AES round. The fastest Rambus AES SCA protected core has no overhead comparing to regular unprotected cores, outperforming competing solutions by a factor of 2.
The countermeasures are extensively validated using Test Vector Leakage Assessment methodology and show no leakage beyond 100 million operations (or 10 for smaller configurations). This results in a core that is protected against side-channel attacks beyond 1 billion operations. The FIA-resistant core detects faults that are injected by, for example, lasers or EM pulses.
Solution Offerings
Features
Deliverables
Features
- Accelerates AES according to FIPS-197 supporting all key sizes
- NIST SP 800-38A: Recommendation for Block Cipher Modes of Operation
- NIST SP 800-38B Block Cipher with Cipher-based Message Authentication Code (CMAC)
- NIST SP 800-38C Block Cipher with Counter with Cipher Block Chaining-Message Authentication Code (CCM)
- NIST SP 800-38D Block Cipher with Galois/Counter Mode (GCM)
- NIST SP 800-38E XEX-based tweaked-codebook (XTS)
- Common Criteria v3.1 ISO/IEC 15408-1/-2/-3, certificate CC-22-0397779 2022-07-29, EAL4+ AVA_VAN.5, ALC_DVS.2, ATE_DPT.2
- SCA Test Vector Leakage Assessment shows no leakage beyond 100 million operations
Deliverables
Complete Documentation
- Integration guide
- Reference manual
RTL Package
- Verilog RTL for synthesis and simulation
- Standard EDA tool flow scripts and support files
- Verification test bench and test vectors
Protecting Data and Devices Now and in the Quantum Computing Era
Quantum computing is being pursued across industry, government and academia with tremendous energy and is set to become a reality in the not-so-distant future. Once sufficiently large quantum computers exist, traditional asymmetric cryptographic methods for key exchange and digital signatures will be broken. Many initiatives have been launched throughout the world to develop and deploy new quantum-resistant cryptographic algorithms, known as Post-Quantum Cryptography (PQC).
From the blog
Resources
Webinars
IME-IP-341 Inline Memory Encryption Engine
IME-IP-341 Inline Memory Encryption Engine
IThe Rambus IME-IP-341 is an SoC-ready, in-line memory encryption engine using AES/SM4 ciphers with XTS/ECB/Bypass as modes of operation. It incorporates multi-stream, multi-algorithm support required for supporting multiple virtual machines (e.g., Realms in ARMv9). It supports configurable protection of different memory regions (up to 32) with separate individual keys mapping to individual regions (e.g., PAS in MPE ARMv9).
The IME-IP-341 provides (optional) protection against power-analysis side-channel attacks by incorporating Differential Power Analysis (DPA) countermeasures within the cipher primitives. Additionally, Datapath Integrity (DI) using ECC based SRAMs with (optional) parity protection in the cipher datapath provides robustness against random errors, ensuring operation under stringent operating conditions in advanced technology nodes. For CMVP certification IME-IP-341 uses a CAVP certified cipher engine and (optional) built in known answer self-test (KAT).
How the IME-IP-341 Engine Works
The Rambus IME-IP-341 is an inline memory encryption engine for protection of off-chip memory. The programming for the security attributes and keys per region is programmed by a dedicated AMBA interface towards trusted subsystem. At the start, different memory regions (up to 32) can be programmed as per different security policies of the system.
Once the IP is programmed and initialized, it acts as a transparent datapath engine between the SoC bus and DDR controller. It also includes functionality to convert an encryption key into its equivalent decryption. Zeroization, and startup behavior is supported in compliance with MPE engine requirements for ARMv9. The IME-IP-341 supports programmable sector size (default is 64B, same as a typical cache line width and a typical DDR burst size).
Solution Offerings
Features
Deliverables
Features
- 128/512-bit (16-byte) encryption and decryption per clock cycle throughput
- Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
- Read-modify-write supporting narrow burst access.
- Zeroization and support for memory initialization
- Latency: <28 clock cycles for unloaded READ
- AMBA AXI4 complaint 128/512-bit data and 32-bit address channel interface (for Master and Slave integration)
- AMBA APB complaint 32-bit control interface
- Interrupts and internal buffer status flags
- Debug and internal errors
- ECC protection for internal SRAMs
- Zeroization and reset
- CAVP certified AES-XTS crypto core
- FIPS-197, IEEE-P1619/D16, FIPS 140-3 and NIST-SP800-38 standards
Deliverables
- Packages
- Documentation
- Tools and scripts
- Integration support
Secure Networking Basics: MACsec, IPsec, and SSL/TLS/DTLS
The MACsec, IPsec and SSL/TLS/DTLS protocols are the primary means of securing data in motion (communicated between connected devices). These protocols can be anchored in hardware or implemented in software as part of an end-to-end security architecture. This white paper provides fundamental information on each of these protocols including their interrelationships and use cases.
Webinars
Silicon IP
Silicon IP
High-performance interface and certified security solutions engineered for your success
With a rich history of innovation spanning over three decades in delivering state-of-the-art Silicon IP solutions, our commitment to support our customers from concept to launch sets us apart. Our trusted expertise, unwavering support, and reliable products empower our customers to accelerate their time to market while minimizing risk and maximizing success.
Our portfolio of Silicon IP solutions includes a broad array of high-performance interface and certified security solutions to meet the stringent demands of emerging applications.
Product Families
Interface IP
Our state-of-the-art interconnect and memory interface IP consists of digital controller IP for PCIe®, CXL®, HBM, GDDR and DDR standards. We also offer digital controller IP for the LPDDR and MIPI® standards, as well as a suite of Video Compression and Forward Error Correction IP.
Security IP
Our security IP protects hardware and data at rest, in motion and in use for a broad range of applications from data center to IoT. We offer certified security IP solutions tailored to meet the requirements of industry and government standards.
Explore Our IP Catalog
| Part Number | Short Description | Keywords | ASIC | FPGA | Product Brief | ||||
|---|---|---|---|---|---|---|---|---|---|
| Silicon IP | Security | 3DES | Cipher Accelerator | 3DES-IP-16 | Rambus 3DES ECD/CBC Accelerator | 3DES, ECB, CBC | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-AE-16-DPA(-FIA) | Rambus AES Authenticated Encryption Accelerator, 16 Sbox, DPA or DPA and FIA | AES, 16 Sbox, DPA,FIA | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-AE-32-DPA(-FIA) | Rambus AES Authenticated Encryption Accelerator, 32 Sbox, DPA or DPA and FIA. CC EAL4+ certified | AES, 32 Sbox, DPA, FIA CC EAL4+ certified | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-IP-36 | Rambus AES ECB/CBC/CTR Accelerator | AES Accelerator , high-speed, high-performance, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-IP-37 | Rambus AES Key Wrap Engine | AES, key-wrap high-speed, high-performance, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-IP-38 | Rambus AES GCM/XTS Engine | AES, GCM, LRW, XTS, high-speed, high-performance, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-IP-39 | Rambus AES “All Modes” Accelerator | AES, CCM, high-speed, high-performance, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | AES-IP-61 | Rambus AES-GCM Pipeline | AES-GCM-GMAC Accelerator, AES-GCM, AES-CTR mode, GHASH | 1 | ||
| Silicon IP | Security | ARC4 | Cipher Accelerator | ARC4-IP-44 | Rambus ARC4 Stream Cipher Accelerator | IP, security, ARC4, crypto, cipher, encryption, decryption, RC4 | 1 | 1 | |
| Silicon IP | Security | ASCON | Crypto Algorithm Accelerator | ASCON-IP-41 | Rambus ASCON Lightweight Crypto Algorithm Accelerator | ASCON | 1 | 1 |  |
| Silicon IP | Security | Cipher Accelerator | QSE-IP-86 | Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) | Quantum Safe Cryptography, Post-Quantum Cryptography, PQC, ML-KEM, ML-DSA, CRYSTALS-Kyber, CRYSTALS-Dilithium | 1 | 1 | | |
| Silicon IP | Security | Cipher Accelerator | QSE-IP-86 DPA | Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA | Quantum Safe Cryptography, Post-Quantum Cryptography, PQC, ML-KEM, ML-DSA, CRYSTALS-Kyber, CRYSTALS-Dilithium | 1 | 1 | | |
| Silicon IP | Interconnect | PCIe | Add-on Core | AXI DMA Back-End Core | Rambus AXI DMA Back-End Core | AXI DMA Back-End Core | 1 | 1 | |
| Silicon IP | Interconnect | PCIe | Add-on Core | AXI Interface Core | Rambus AXI Interface Core | AXI, AMBA | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | CC-312 Security Module | Rambus CC-312 CryptoCell Security Module for Arm Cortex-M TrustZone-based IoT Edge Devices and Sensors | Security Engine, CryptoCell, Arm, Cortex-M, TrustZone | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | CC-712 Security Module | Rambus CC-712 CryptoCell Security Module for Arm Cortex-A TrustZone-based IoT Servers and Gateways | Security Engine, CryptoCell, Arm, Cortex-A, TrustZone | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | CC-713 Security Module | Rambus CC-713 CryptoCell Security Module for Arm Cortex-A TrustZone-based IoT Servers and Gateways for the China Market | Security Engine, CryptoCell, Arm, Cortex-A, TrustZone | 1 | 1 | |
| Silicon IP | Interconnect | CCIX 1.1 | Controller | CCIX 1.1 Controller | Rambus CCIX 1.1 Controller | PCIe, PCI Express, PCIe 5.0, PCI Express Gen4, PCIe Gen 4, PCIe 4.0, PCI Express Gen6 | 1 | 1 | |
| Silicon IP | Interconnect | CCIX 1.1 | Controller | CCIX 1.1 Controller with AXI | Rambus CCIX 1.1 Controller with AMBA AXI interface | PCIe, CCIX, AMBA, AXI | 1 | 1 | |
| Silicon IP | Security | ChaCha20 | Cipher Accelerator | ChaCha-13 | Rambus ChaCha20 Engine | ChaCha, ChaCha20, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | CI-300P-C Security Module | Rambus CI-300P-C CryptoIsland Security Module for Secure Element Devices such as iSim, 5G Modems, Mobile App Processors | Security Engine, CryptoIsland, Arm, Secure Element | 1 | 1 | |
| Silicon IP | Security | AES, SHA-2 | Cipher Accelerator | CRYPT-IP-120 | Rambus Low-power HMAC SHA AES Crypto Engine | HMAC SHA AES Accelerator, AES, SHA, HMAC, GCM, DMA, AHB | 1 | 1 | |
| Silicon IP | Security | Many | Anti-Counterfeiting | CryptoFirewall Consumable Core | Rambus CryptoFirewall Consumable Core | Anti-counterfeiting security core, Consumable core | 1 | | |
| Silicon IP | Security | Many | Anti-Counterfeiting | CryptoFirewall Verfier Core | Rambus CryptoFirewall Verfier Core | Anti-counterfeiting security core, Verifier core | 1 | | |
| Silicon IP | Interconnect | CXL 2.0/1.1 | Controller | CXL 2.0 Controller | Rambus Compute Express Link (CXL) 2.0 Controller | CXL, Compute Express Link | 1 | 1 | |
| Silicon IP | Interconnect | CXL 3.1 | Controller | CXL 3.1 Controller | Rambus Compute Express Link (CXL) 3.1 Controller | CXL, Compute Express Link | 1 | 1 | |
| Silicon IP | Interconnect | CXL 3.1 | Controller | CXL 3.1 Controller with AXI | Rambus Compute Express Link (CXL) 3.1 Controller with AXI | CXL, Compute Express Link | 1 | 1 | |
| Silicon IP | Interconnect | CXL 2.0/1.1 | Controller | CXL 2.0 Controller with AXI | Rambus Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface | CXL, Compute Express Link, AXI | 1 | 1 | |
| Silicon IP | Memory Interface | DDR3 | Controller | DDR3 Memory Controller | Rambus DDR3 Memory Controller | DDR3 Controller, DDR3 | 1 | | |
| Silicon IP | Memory Interface | DDR4 | Controller | DDR4 Memory Controller | Rambus DDR4 Memory Controller | DDR4 Controller, DDR4 | 1 | | |
| Provisioning | Security | Security | Secure Provisioning | Device Key Management | Rambus Device Key Management Platform | Provisioning, device identification, root key storage, Root of Trust | | ||
| Silicon IP | Forward Error Correction | DisplayPort 1.4 | FEC Receiver | DisplayPort 1.4 FEC Reciever | Rambus DisplayPort 1.4 FEC Receiver | DisplayPort, FEC, Receiver, Forward Error Correction | 1 | 1 | |
| Silicon IP | Forward Error Correction | DisplayPort 1.4 | FEC Transmitter | DisplayPort 1.4 FEC Transmitter | Rambus DisplayPort 1.4 FEC Transmitter | DisplayPort, FEC, Transmitter, Forward Error Correction | 1 | 1 | |
| Silicon IP | Forward Error Correction | DisplayPort 1.4 | FEC Transmitter | DisplayPort 1.4 FEC Transmitter | Rambus DisplayPort 1.4 FEC Transmitter for Automotive, ASIL-B | DisplayPort, FEC, Transmitter, Forward Error Correction | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | DMA Back-End Core | Rambus DMA Back-End Core | DMA Back-End Core | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | DMA Back-End Driver | Rambus DMA Back-End Driver | DMA Driver, dma, driver | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | DMA Bridge Core | Rambus High-performance PCIe-AXI Bridge and/or scatter-gather DMA | PCIe-AXI Bridge , DMA | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | DMA Driver | Rambus Windows & Linux Drivers for the DMA Core | DMA Driver, dma, driver | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA & FI Resistant AES-32 Crypto Core | Rambus DPA and Fault Injection Resistant AES-32 Cryptographic Core | Rambus DPA and Fault Injection Resistant AES-32 Cryptographic Core | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA & FI Resistant AES-AE Crypto Core | Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Core | Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Core | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA & FI Resistant AES-ECB Crypto Core | Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Core | Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Core | 1 | 1 | |
| Silicon IP | Security | PKE | Public Key Accelerator | DPA & FI Resistant PKE Crypto Accelerator Core | Rambus DPA & Fault Injection Resistant PKE Cryptographic Accelerator Core | Rambus DPA and Fault Injection Resistant PKE 64×64 Cryptographic Accelerator Core | 1 | 1 | |
| Silicon IP | Security | 3DES | Cipher Accelerator | DPA Resistant 3DES (ECB) Crypto Accelerator Core | Rambus 3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core | Rambus Cryptographic Accelerator Core 3DES-ECB | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA Resistant AES Core | Rambus DPA Resistant AES Core | AES, DPA Resistant, cryptography | 1 | | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA Resistant AES-AE Crypto Accelerator Core | Rambus AES (ECB-CBC-CFB-CTR-GCM), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores | Rambus Cryptographic Accelerator Core AES-AE | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA Resistant AES-ECB Crypto Accelerator Core | Rambus AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores | Rambus Cryptographic Accelerator Core AES-ECB | 1 | 1 | |
| Silicon IP | Security | AES | Cipher Accelerator | DPA Resistant AES-FBC Crypto Accelerator Core | Rambus AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores | Rambus Cryptographic Accelerator Core AES-FBC | 1 | 1 | |
| Silicon IP | Security | 3DES | Cipher Accelerator | DPA Resistant Crypto Accelerator Core 3DES-ECB | Rambus DPA Resistant Cryptographic Accelerator Core 3DES-ECB | Rambus DPA Resistant Cryptographic Accelerator Core 3DES-ECB | 1 | 1 | |
| Silicon IP | Security | ChaCha20 | Cipher Accelerator | DPA Resistant Crypto Accelerator Core ChaCha20 | Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 | Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 | 1 | 1 | |
| Silicon IP | Security | ChaCha20 | Cipher Accelerator | DPA Resistant Crypto Accelerator Core ChaCha20 | Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 | Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 | 1 | 1 | |
| Silicon IP | Security | RNG | Random Number Generator | DPA Resistant Crypto Accelerator Core RBG | Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) | Rambus DPA Resistant Cryptographic Accelerator Core RBG (NRBG+DRBG) | 1 | 1 | |
| Silicon IP | Security | HMAC SHA-2 | HMAC Accelerator | DPA Resistant HMAC-SHA-2 Crypto Accelerator Core | Rambus HMAC-SHA-2 (224/256/384/512) 100 Million Trace DPA Resistant Cryptographic Accelerator Cores | Rambus Cryptographic Accelerator Core HMAC-SHA-2 | 1 | 1 | |
| Silicon IP | Security | PKE | Cipher Accelerator | DPA Resistant PKE Crypto Accelerator Core | Rambus DPA Resistant Cryptographic Accelerator Core | Rambus DPA Resistant Cryptographic Accelerator Core PKE | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | ECC Core | Rambus ECC Core | error correction code | 1 | 1 | |
| Software Library | Security | IPsec, MACsec | Software Library | FIPS Cryptographic Libraries | Rambus FIPS 140-2 and FIPS 140-3 validated cryptographic libraries | FIPS 140-2, FIPS 140-3, cryptographic libraries | |||
| Software Toolkit | Security | TLS | Software Toolkit | FIPS TLS Toolkit | Rambus FIPS compliant TLS toolkit | | |||
| Silicon IP | Memory Interface | GDDR6 | Controller | GDDR6 Memory Controller | Rambus GDDR6 Controller | GDDR6 Controller, GDDR 6 Controller | 1 | | |
| Silicon IP | Memory Interface | GDDR7 | Controller | GDDR7 Memory Controller | Rambus GDDR7 Controller | GDDR7 Controller, GDDR 7 Controller, GDDR7 Memory Controller | 1 | | |
| Debug and Test | Interconnect | PCIe 5.0 / 32G | PCIe Test and Development | Gen5Endpoint | Rambus Gen5Endpoint reference plaform for prototyping and development of PCIe 5.0 hosts/root port devices | PCI Express, PCIe 5.0 | | ||
| Debug and Test | Interconnect | PCIe 5.0 / 32G | PCIe Test and Development | Gen5Host | Rambus Gen5Host reference plaform for prototyping and development of PCIe 5.0 endpoint devices | PCI Express, PCIe 5.0 | | ||
| Silicon IP | Security | HMAC SHA-3, SHA-2 | Hash/HMAC Accelerator | HASH-IP-57 | Rambus SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerator | MD5/SHA-1/SHA-2 Accelerator, SHA, SHA-1, MD5, SHA-2, SHA-256, SHA-224, SHA-384, SHA-512, hashing, silicon, SoC, hash, sha, authentication, security | 1 | 1 | |
| Silicon IP | Memory Interface | HBM2/2E | Controller | HBM2/2E Controller Core V2 | Rambus HBM2/2E Memory Controller Core | HBM Controller, HBM, Controller, Memory Controller, DRAM Controller, HBM2E Controller, HBM Gen 2 Controller, HBM Gen 2E Controller | 1 | 1 | |
| Silicon IP | Memory Interface | HBM3/3E | Controller | HBM3E/3 Memory Controller | Rambus HBM3 Memory Controller | HBM Controller, HBM, Controller, Memory Controller, DRAM Controller, HBM3 Controller, HBM3E Controller, HBM 3 Controller, HBM Gen 3 Controller | 1 | 0 | |
| Silicon IP | Memory Interface | HBM4/4E | Controller | HBM4 Memory Controller | Rambus HBM4 Memory Controller | HBM Controller, HBM, Controller, Memory Controller, DRAM Controller, HBM4 Controller, HBM 4 Controller, HBM Gen 4 Controller | 1 | 1 | |
| Silicon IP | Memory Interface | HBM4/4E | Controller | HBM4E Memory Controller | Rambus HBM4E Memory Controller | HBM Controller, HBM, Controller, Memory Controller, DRAM Controller, HBM4E Controller, HBM 4E Controller, HBM Gen 4E Controller | 1 | 0 | |
| Silicon IP | Forward Error Correction | HDMI 2.1 | FEC Receiver | HDMI 2.1 FEC Receiver | Rambus HDMI 2.1 FEC Receiver | HDMI, FEC, Receiver, Forward Error Correction | 1 | 1 | |
| Silicon IP | Forward Error Correction | HDMI 2.1 | FEC Transmitter | HDMI 2.1 FEC Transmitter | Rambus HDMI 2.1 FEC Transmitter | HDMI, FEC, Transmitter, Forward Error Correction | 1 | 1 | |
| Silicon IP | Security | SHA-3, SHAKE | HMAC Accelerator | HMAC-IP-59 | Rambus SHA-3, SHAKE, cSHAKE, SHA-2, SHA-1, SM3, MD5 Hash-based HMAC and KMAC Accelerator | SHA-3, SHAKE, cSHAKE, SHA-2, SHA-1, SM3, MD5 Hash-based HMAC, KMAC | 1 | 1 | |
| Silicon IP | Security | HMAC SHA-2 | HMAC Accelerator | HMAC-SHA-256-512-DPA | Rambus HMAC SHA-2 engine, 224, 256, 384 & 512 Mode, DPA | HMAC, SHA, SHA-1, MD5, SHA-2, SHA-256, SHA-224, SHA-384, SHA-512, hashing, silicon, SoC, hash, sha, authentication, security | 1 | 1 | |
| Silicon IP | Security | HMAC SHA-2 | HMAC Accelerator | HMAC-SHA-256-DPA | Rambus HMAC SHA-2 engine, 224 & 256 Mode, DPA | HMAC, SHA, SHA-1, MD5, SHA-2, SHA-256, SHA-224, SHA-384, SHA-512, hashing, silicon, SoC, hash, sha, authentication, security | 1 | 1 | |
| Silicon IP | Security | AES | Inline Cipher Engine | ICE-338-AES-DPA | Rambus AES Inline Cipher Engine, DPA | Inline Cipher Engine, AES, DPA | 1 | 1 | |
| Silicon IP | Security | AES | Inline Cipher Engine | ICE-338-AES-DPA | Rambus AES Inline Cipher Engine, DPA | AES, Inline Cipher, DPA | 1 | 1 | |
| Silicon IP | Security | SM4 | Inline Cipher Engine | ICE-338-SM4-DPA | Rambus SM4 Inline Cipher Engine, DPA | Inline Cipher Engine, SM4, DPA | |||
| Silicon IP | Security | SM4 | Inline Cipher Engine | ICE-338-SM4-DPA | Rambus SM4 Inline Cipher Engine, DPA | SM4, Inline Cipher, DPA | 1 | 1 | |
| Silicon IP | Security | AES | Inline Cipher Engine | ICE-IP-338 | Rambus Inline Cipher Engine for Memory Encryption. AES-XTS/GCM, SM4-XTS/GCM | Inline Ciper Engine, AES-XTS, AES-GCM, SM4-XTS, SM4-GCM, XTS, GCM, DPA | 1 | 1 | |
| Silicon IP | Security | AES, SM4 | Inline Cipher Engine | ICE-IP-339 | Rambus Inline Cipher Engine with AXI, for Memory Encryption. AES-XTS/GCM, SM4-XTS/GCM | Inline Ciper Engine, AES-XTS, AES-GCM, SM4-XTS, SM4-GCM, XTS, GCM, DPA, AXI | 1 | 1 | |
| Silicon IP | Security | PCIe, CXL, NVMe | Inline Cipher Engine | ICE-IP-63 | Rambus Inline Cipher Engine for PCIe, CXL, NVMe, 5G FlexE link integrity and IDE with AES-GCM | Inline Cipher Engine for PCIe, CXL, NVMe, 5G FlexE link, IDE, AES-GCM | 1 | 1 | |
| Chips | Memory Interface | DDR4 | Data Buffer | iDDR4DB2-GS02 | Rambus DDR4 Data Buffer 3200 MT/s data rate | DDR4, RDIMM, LRDIMM, DB | | ||
| Chips | Memory Interface | DDR4 | Registering Clock Driver | iDDR4NVRCD2-GS03 | Rambus DDR4 Registering Clock Driver 3200 MT/s data rate for non-volatile memory | DDR4, NVDIMM, RCD | | ||
| Chips | Memory Interface | DDR4 | Registering Clock Driver | iDDR4RCD-GS02 | Rambus DDR4 Registering Clock Driver 3200 MT/s data rate | DDR4, RDIMM, LRDIMM, RCD | | ||
| Silicon IP | Security | AES | Inline Memory Encryption Engine | IME-IP-340 | Rambus Inline Memory Encryption Engine for FPGA, AES-GCM | Inline Memory Encryption, IME, FPGA, AES-GCM, DPA | 1 | | |
| Silicon IP | Security | AES, SM4 | Inline Memory Encryption Engine | IME-IP-341 | Rambus Inline Memory Encryption Engine for ASIC, AES-XTS/GCM amd SM4-XTS/GCM | Inline Memory Encryption, IME, AES-XTS, AES-GCM, SM4-XTS, SM4-GCM, XTS, GCM, DPA | 1 | | |
| Software Toolkit | Security | IPsec | Software Toolkit | IPsec Toolkit | Rambus IPsec software toolkit | ipsec, toolkit | | ||
| Silicon IP | Security | Kasumi | Cipher Accelerator | Kasumi-IP-06 | Rambus 3GPP Kasumi Accelerator | Kasumi, 3GPP, f8, f9, encryption, decryption, crypto, security, cryptographic, cipher | 1 | 1 | |
| Silicon IP | Memory Interface | LPDDR4X/4 | Controller | LPDDR4X/4 Memory Controller Core | Rambus LPDDR4X/4 Controller Core | LPDDR4 Controller, LPDDR4, LPDDR4X Controller, LPDDR4X, SDRAM, memory Controller | 1 | 1 | |
| Silicon IP | Memory Interface | LPDDR5T/5X/5 | Controller | LPDDR5T/5X/5 Memory Controller Core | Rambus LPDDR5T/5X/5 Controller Core | LPDDR5 Controller, LPDDR5, LPDDR5X Controller, LPDDR5X, LPDDR5T Controller, LPDDR5T, SDRAM, memory Controller | 1 | 1 | |
| Silicon IP | Memory Interface | LPDDR5T/5X/5, LPDDR4X/4 | Controller | LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller Core | Rambus LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller Core | LPDDR4 Controller, LPDDR4, LPDDR4X Controller, LPDDR4X, LPDDR5 Controller, LPDDR5, LPDDR5X Controller, LPDDR5X, LPDDR5T Controller, LPDDR5T, SDRAM, memory Controller | 1 | 1 | |
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-160 | Rambus 1G to 100G Single-Port MACsec Engine with FIFO Interface | MACsec, security, accelerators, FIFO, 100Gbps, Ethernet | 1 | 1 | |
| Silicon IP | Security | UET-TSS | Protocol Engine | UET-TSS-IP-69 | Rambus multi-channel Ultra Ethernet TSS transformation engine providing full line-rate throughput up to 1.6T | UET-TSS, Ultra Ethernet Security | 1 | | |
| Silicon IP | Security | UET-TSS | Protocol Engine | UET-TSS-IP-369 | Rambus multi-channel Ultra Ethernet TSS complete layer providing full line-rate throughput up to 1.6T | UET-TSS, Ultra Ethernet Security | 1 | | |
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-362 | Rambus Automotive-grade 10M to 25G Single-Port MACsec Engine with xMII, GMII and XGMII support | MACsec, security, accelerators, MII, RMII, GMII, XGMII, 25Gbps, TSN, IEEE802.3br, ISO 26262, Automotive | 1 | 1 | |
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-162 | Rambus Automotive-grade 10M to 25G Single-Port MACsec Engine | MACsec, Inline, security, crypto, protocol, high-speed, high-performance, Frame, accelerator, crypto, automotive | 1 | 1 | |
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-161 | Rambus 1G to 50G Single-Port MACsec Engine with TSN Support | MACsec, Inline, security, crypto, protocol, high-speed, high-performance, Frame, accelerator, crypto | | ||
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-364 | Rambus 1.6T/3.2T Multi-Channel MACsec Engine | MACsec, security, accelerator, 1.6Tbps, 3.2Tbps, 800Gpbs, optional IPsec security | | ||
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-363 | Rambus 1.6T/3.2T Multi-Channel MACsec Classifier | MACsec, security, classifier, 1.6Tbps, 3.2Tbps, 800Gpbs, optional IPsec security | | ||
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-164 | Rambus 800G Multi-Channel MACsec Engine | MACsec, security, accelerator, 100Gbps to 800Gbps, optional ClearTags and other classification features, Cisco extensions | 1 | 1 | |
| Silicon IP | Security | MACsec | Protocol Engine | MACsec-IP-361 | Rambus 1G to 50G Single-Port MACsec Engine with xMII Support | MACsec, security, accelerators, MII, GMII, xMII, 50Gbps, TSN, IEEE802.3br | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Controller | Mem Test Analyzer Core | Rambus Mem Test Analyzer Core | Mem Test Analyzer Core | 1 | 1 | |
| Silicon IP | Interconnect | MIPI CSI-2 Tx and Rx | Controller | MIPI CSI-2 Tx and Rx Controller Core V2 | Rambus MIPI CSI-2 Tx and Rx Controller Core V2 | MIPI CSI-2 Controller , MIPI, CSI-2, CSI2, Controller , mipi | 1 | 1 | |
| Silicon IP | Interconnect | MIPI DSI-2 Tx and Rx | Controller | MIPI DSI-2 Tx and Rx Controller Core | Rambus MIPI DSI-2 Tx and Rx Controller Core | MIPI DSI Controller, DSI-2, DSI2, DSI Controller, MIPI | 1 | 1 | |
| Debug and Test | Interconnect | MIPI | Controller | MIPI Testbench | Rambus MIPI Testbench | MIPI, Testbench | 1 | 1 | |
| Silicon IP | Interconnect | MIPI Testbench | Testbench | MIPI Testbench | Rambus MIPI Testbench | MIPI, CSI-2, DSI-2, Testbench | | ||
| Silicon IP | Memory Interface | DDR | Controller | Multi-Port Front-End | Rambus Multi-Port Front-End | Multi-Port Front-End | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 1.1 | Controller | PCIe 1.1 Controller | Rambus PCIe 1.1 Controller with PHY Interface for PCI Express (PIPE) specification and native user interface support | PCIe, PCI Express, PCIe 1.0, PCI Express Gen4, PCIe Gen 1, AMBA-AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 1.1 | Controller | PCIe 1.1 Controller with AXI | Rambus PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect | PCI Express Controller, PCIe, AXI, PCI Express, DMA, controller, gen4, PCIe 1.0, AMBA, AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 2.1 | Controller | PCIe 2.1 Controller | Rambus PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support | PCIe, PCI Express, PCIe 2.0, PCI Express Gen4, PCIe Gen 2, AMBa-AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 2.1 | Controller | PCIe 2.1 Controller with AXI | Rambus PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect | PCI Express Controller, PCIe, AXI, PCI Express, DMA, controller, gen4, PCIe 2.0, AMBA, AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 3.1 | Controller | PCIe 3.1 Controller | Rambus PCIe 3.1, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support | PCI Express Controller, PCIe, PCI Express, 3.0, 2.0, 1.1, IP, endpoint, root, switch, gen3 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 3.1 | Controller | PCIe 3.1 Controller with AXI | Rambus PCIe 3.1, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface | PCI Express Controller, PCIe, AXI, PCI Express, DMA, controller, gen3 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 4.0 / 16G | Controller | PCIe 4.0 Controller | Rambus PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features | PCIe, PCI Express, PCIe 4.0, PCI Express Gen4, PCIe Gen 4, | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 4.0 / 16G | Controller | PCIe 4.0 Controller with AXI | Rambus PCIe 4.0 Controller with AMBA AXI interface | PCI Express Controller, PCIe, AXI, PCI Express, DMA, controller, gen4, PCIe 4.0, AMBA, AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / 32G | Controller | PCIe 5.0 Controller | Rambus PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features | PCIe, PCI Express, PCIe 5.0, PCI Express Gen5, PCIe Gen 5, | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / 32G | Controller | PCIe 5.0 Controller with AXI | Rambus PCIe 5.0 Controller with AMBA AXI interface | DMA Engine, DMA, PCIe, PCI Express, FPGA, Altera, Xilinx, DMA AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / 32G | Controller | PCIe 5.0 Multi-port Switch | Rambus PCIe 5.0 Customizable Embedded Multi-port Switch | PCIe, Switch, Switch IP, Switch Core, Multi-port PCIe Switch, PCI Express | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 6.1 / 64G and PCIe | Controller | PCIe 6.1 Controller | Rambus PCIe 6.1 Controller | PCIe 6.1, PCI express 6.1 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 7.0 | Controller | PCIe 7.0 Controller | Rambus PCIe 7.0 Controller | PCIe 7.0, PCI Express 7.0 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 7.0 | Controller | PCIe 7.0 Controller with AXI | Rambus PCIe 7.0 Controller with AXI | PCIe 7.0, PCI Express 7.0 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 7.0 | Controller | PCIe 7.0 Retimer Controller | Rambus PCIe 7.0 Retimer Controller | PCIe 7.0, PCI Express 7.0, Retimer | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 7.0 | Controller | PCIe 7.0 Switch | Rambus PCIe 7.0 Switch | PCIe 7.0, PCI Express 7.0, Switch | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 6.3 | Controller | PCIe 6.3 Switch | Rambus PCIe 6.3 Switch | PCIe 6.3, PCI Express 6.3, Switch | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 6.3 / 64G and PCIe | Controller | PCIe 6.3 Controller | Rambus PCIe 6.3 Controller with AXI interface | PCIe 6.3, PCI express 6.3 | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 6.3 / 64G | Retimer Controller | PCIe 6.3 Retimer Controller | Rambus PCIe 6.3 Retimer Controller | PCIe 6.3, PCI express 6.3, Retimer | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / USB4 | Controller | PCIe Controller for USB4 | Rambus PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling | PCIe, USB4, Device, Host | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / USB4 | Controller | PCIe Controller for USB4 with AXI | Rambus PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface | PCIe, USB4, Device, Host, AMBA, AXI | 1 | 1 | |
| Silicon IP | Interconnect | PCIe Controller Testbench | Controller | PCIe Controller Testbench | Rambus PCIe Controller Testbench | PCIe Testbench, PCI Express Testbench | 1 | 1 | |
| Silicon IP | Interconnect | PCIe 5.0 / USB4 | Controller | PCIe Multi-port Switch for USB4 | Rambus PCIe Switch for USB4 Hubs, Hosts and Devices | PCIe, Switch, Switch IP, Switch Core, Multi-port PCIe Switch, PCI Express, USB4 | 1 | 1 | |
| Silicon IP | Security | PKE | Public Key Accelerator | PKA-IP-150 | Rambus RSA/ECC Public Key Accelerators with TRNG and AHB | public key accelerator, PKI, RSA, ECC, TRNG, AHB | 1 | 1 | |
| Silicon IP | Security | PKE | Public Key Accelerator | PKA-IP-28 | Rambus Public Key accelerator Engine | public key accelerator, PKI, security | 1 | 1 | |
| Silicon IP | Security | PKE | Public Key Accelerator | PKE-IP-85-DPA(-FIA) | Rambus Public Engine with DPA or with DPA and FIA | public key accelerator, PKI, security, TRNG, random, number | 1 | 1 | |
| Silicon IP | Security | PKE | Ultra-Fast Public Key Engine | PKE-IP-85f | Rambus Ultra-Fast Public Key Engine | public key accelerator, PKI | 1 | 1 | |
| Silicon IP | Security | PKE | Farm of Ultra-Fast Public Key Engines | PKE-IP-85f-x | Rambus Farm of x * Ultra-Fast Public Key Engines | public key accelerator, PKI, Farm | 1 | 1 | |
| Silicon IP | Security | PKE | Public Key Accelerator Farm | PKI-IP-154 | Rambus Public Key Accelerator Farm Engine with TRNG and AHB | Public Key Infrastructure, Public Key Accelerator, RSA, PKI, security, TRNG, random, number, AES, AHB, Farm | 1 | 1 | |
| Silicon IP | Security | Poly1305 | Hash/HMAC Accelerator | POLY-IP-53 | Rambus Poly1305-based MAC Accelerator | Poly, poly1305, hashing, silicon, SoC, authentication, security | 1 | 1 | |
| Silicon IP | Security | IPsec/TLS/DTLS/SSL | Protocol Engine | Protocol-IP-196 | Rambus 10G Multi-Protocol Engine with Classifier, Look-Aside | Security Protocol Engine, Flow-Through Packet Engine, inline, packet processing, security, IP, crypto, encryption, packet classification, Ipsec, SSL, TLS, DTLS, 3GPP, MACsec | 1 | 1 | |
| Silicon IP | Security | IPsec/TLS/DTLS/SSL | Protocol Engine | Protocol-IP-197 | Rambus 100G Multi-Protocol Engine with Classification, Look-Aside and Inline | Security Protocol Engine, Flow-Through Packet Engine, inline, packet processing, security, IP, crypto, encryption, packet classification, IPsec, SSL, TLS, DTLS, CAPWAP, 3GPP, MACsec, AMBA | 1 | 1 | |
| Silicon IP | Security | IPsec ESP | Protocol Engine | Protocol-IP-67 | Rambus 800G 64-Channel IPsec ESP Transform Engine, AES-GCM, AES-GMAC | IPSec ESP, AES-GCM, AES-GMAC, 800G, time-sliced packet interface | 1 | 1 | |
| Silicon IP | Security | IPsec ESP | Protocol Engine | Protocol-IP-68 | Rambus 100G 64-channel IPsec ESP Transform Engine, AES-GCM, AES-GMAC, 50G ChaCha20/Poly1305 | IPSec ESP, AES-GCM, AES-GMAC, 100G, ChaCha20, Poly1305, time-sliced packet interface | 1 | 1 | |
| Silicon IP | Security | IPsec/TLS/DTLS/SSL | Protocol Engine | Protocol-IP-93 | Rambus Low Power 1G Multi-Protocol Engine | IPSec, TLS, SRTP, SSL, AHB, PLB, Packet, DMA, SA, security, crypto, protocol, low gate count, accelerator, security, crypto | 1 | 1 | |
| Provisioning | Security | Security | Secure Provisioning | Provisioning Platform | Rambus Provisioning Platform | Provisioning, device identification, root key storage, Root of Trust | | ||
| Chips | Memory Interface | DDR5 | Registering Clock Driver | RCD1-G1EX | Rambus DDR5 Registering Clock Driver 4800 MT/s date rate | DDR5, RDIMM, RCD | https://go.rambus.com/ddr5-rcd-4800-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Registering Clock Driver | RCD2-G1B | Rambus DDR5 Registering Clock Driver 5600 MT/s date rate | DDR5, RDIMM, RCD | https://go.rambus.com/ddr5-rcd-5600-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Registering Clock Driver | RCD4-GA0 | Rambus DDR5 Registering Clock Driver 7200 MT/s date rate | DDR5, RDIMM, RCD | https://go.rambus.com/ddr5-rcd-7200-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Registering Clock Driver | RCD3-G1A | Rambus DDR4 Registering Clock Driver 6400 MT/s data rate | DDR5, RDIMM, RCD | https://go.rambus.com/ddr5-rcd-6400-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Silicon IP | Memory Interface | DDR | Add-on Core | Read-Modify-Write Core | Rambus Read-Modify-Write Core | Read-Modify-Write Core | 1 | 1 | |
| Silicon IP | Memory Interface | DDR | Add-on Core | Reorder Core | Rambus Reorder Core | Reorder Core, Memory Interface | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-120 Root of Trust | Rambus RT-120 Firmware-Controlled Root of Trust for IoT and IIoT, sensors and gateways | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-100, Root of Trust RT-120 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-121 Root of Trust | Rambus RT-121 Firmware-Controlled Root of Trust for IoT and IIoT, sensors and gateways for China market | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-121, Root of Trust RT-121 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-130 Root of Trust | Rambus RT-130 Firmware-Controlled Root of Trust for IoT, IoT servers, gateways, edge devices | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-130, Root of Trust RT-130 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-131 Root of Trust | Rambus RT-131 Firmware-Controlled Root of Trust for IoT, IoT servers, gateways, edge devices for China market | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-131, Root of Trust RT-131 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-140 Root of Trust | Rambus RT-140 State-Machine-based Root of Trust for IoT, IIoT and cloud-connected devices, sensors, gateways | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-140, Root of Trust RT-140 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-1660 Root of Trust | Rambus RT-1660 Highly Secure Hardware Programmable Root of Trust Security Processor with DPA and FIA Resistance | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-1660, Root of Trust RT-1660, Rambus Hardware Root of Trust RT-1660, Root of Trust RT-1660, DPA, FIA | 1 | | |
| Silicon IP | Security | Many | Root of Trust | RT-260 Root of Trust | Rambus RT-260 State-Machine-based Root of Trust for IoT, IIoT and cloud-connected devices, sensors, gateways | Security Engine, VaultIP, Root of Trust, Rambus Hardware Root of Trust RT-260, Root of Trust RT-260 | 1 | 1 | |
| Silicon IP | Security | Many | Root of Trust | RT-630-FPGA Root of Trust | Rambus RT-630-FPGA Programmable Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140 | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-630, Root of Trust RT-630, Rambus Hardware Root of Trust RT-630 FPGA, Root of Trust RT-630 FPGA | 1 | | |
| Silicon IP | Security | Many | Root of Trust | RT-640 HSM/Root of Trust | Rambus RT-640 Programmable Embedded Hardware Security Module (HSM) for Automotive ASIL-B | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-640, Root of Trust RT-640, ASIL-B | 1 | | |
| Silicon IP | Security | Many | Root of Trust | RT-641 HSM/Root of Trust | Rambus RT-641 Programmable Embedded Hardware Security Module (HSM) for China Market | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-641, Root of Trust RT-641 | 1 | | |
| Silicon IP | Security | Many | Root of Trust | RT-648 HSM/Root of Trust | Rambus Automotive-grade RT-648 CryptoManager HSM, fully programmable ISO 26262 and ISO 21434 compliant hardware security core with Arm Cortex-M33 Processor | Security Engine, CryptoManager, Root of Trust, HSM, Rambus Hardware Root of Trust, Quantum Safe, OSCAA, SM2, SM3, SM4, ISO 26262, ASIL-B, ISO 21434, Automotive, Arm, Cortex-M33 | 1 | | |
| Silicon IP | Security | Many | Root of Trust | CryptoManager Root of Trust for use with the Caliptra specification | CryptoManager Root of Trust for use with the Caliptra specification, Root of Trust and security orchestration solution for Caliptra-based SoCs | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust, Caliptra, Quantum Safe, DPA, FIA, FIPS 140-3, PSA, SESIP, SM2, SM3, SM4 | 1 | | |
| Silicon IP | Security | Security | Root of Trust | RT-7xx CryptoManager Root of Trust Family | Rambus Automotive-grade RT-7xx CryptoManager HSM, fully programmable ISO 26262 and ISO 21434 compliant hardware security core | Security Engine, CryptoManager, Root of Trust, HSM, Rambus Hardware Root of Trust RT-7xx, Quantum Safe, DPA, FIA, OSCAA, SM2, SM3, SM4, ISO 26262, ASIL-B, ASIL-D, ISO 21434, RT-730B, RT-731B, RT-734B, RT-760D, RT-761D, RT-764D, Automotive | 1 | https://go.rambus.com/rt-7xx-embedded-hsm-family-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | |
| Silicon IP | Security | Security | Root of Trust | RT-6xx CryptoManager Root of Trust Family | Rambus RT-6xx CryptoManager Root of Trust, fully programmable FIPS 140-3 compliant hardware security core | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-6xx, Root of Trust RT-630, FIPS-140, Caliptra, Quantum Safe, DPA, FIA, OSCAA, SM2, SM3, SM4, RT-631, RT-634, RT-635, RT-639, RT-660, RT-661, RT-664, RT-669, RT-1660, RT-1664 | 1 | https://go.rambus.com/cryptomanager-rt-6xx-root-of-trust-family-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | |
| Silicon IP | Security | Security | Root of Trust | CH-7xx CryptoManager Hub Family | Rambus Automotive-grade CH-7xx NIST CAVP hardware classic cryptographic accelerators (AES, SHA-2, SHA-3, RSA, ECC) with a NIST certified TRNG | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust, CryptoManager Hub, Quantum Safe, DPA, FIA, OSCCA, SM2, SM3, SM4, CH-730B, CH-731B, CH-734B, CH-760D, CH-761D, CH-764D, Automotive | 1 | | |
| Silicon IP | Security | Security | Root of Trust | CH-6xx CryptoManager Hub Family | Rambus CH-6xx NIST CAVP hardware classic cryptographic accelerators (AES, SHA-2, SHA-3, RSA, ECC) with a NIST certified TRNG | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust, CryptoManager Hub, Quantum Safe, DPA, FIA, OSCCA, SM2, SM3, SM4, CH-630, CH-631, CH-634, CH-660, CH-661, CH-664 | 1 | | |
| Silicon IP | Security | Many | Root of Trust | RT-660-FPGA Root of Trust | Rambus RT-660-FPGA DPA-Resistant Hardware Programmable Root of Trust Security Processor with DPA and FIA Resistance | Security Engine, CryptoManager, Root of Trust, Rambus Hardware Root of Trust RT-660, Root of Trust RT-660, Rambus Hardware Root of Trust RT-660 FPGA, Root of Trust RT-660 FPGA | 1 | | |
| Software Toolkit | Security | Many | Software Toolkit | Secure Boot | Rambus secure boot solution | secure boot, crypto, security | |||
| Silicon IP | Security | SM3 | Hash/HMAC Accelerator | SM3-IP-52 | Rambus SM3 Engine | Sm3, hashing, silicon, SoC, authentication, security | 1 | 1 | |
| Silicon IP | Security | SM4 | Cipher Accelerator | SM4-IP-12 | Rambus SM4 ECB/CBC/CTR Accelerator | SM4, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Silicon IP | Security | SM4 | Cipher Accelerator | SM4-IP-40 | Rambus SM4 “All Modes” Accelerator | SM4, XTS, DDR, Encryption, SM, OSCCA | 1 | 1 | |
| Silicon IP | Security | SNOW | Cipher Accelerator | SNOW-IP-46 | Rambus 3GPP SNOW Accelerator | SNOW3G, SNOW, 3GPP, high-speed, high-performance, encrypt, decrypt, core, accelerator, security, crypto, cipher | 1 | 1 | |
| Chips | Memory Interface | DDR5 | SPD Hub with Internal Temperature Sensor | SPD5118-G1B | Rambus DDR5 SPD Hub with Internal Temperature Sensor | DDR5, RDIMM, RCD, SPD Hub, UDIMM, SODIMM | https://go.rambus.com/ddr5-spd-hub-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Silicon IP | Security | TRNG | True Random Number Generator | TRNG-IP-76 | Rambus FIPS-certified TRNG, SP800-90A/B/C Certified, with DRBG | RNG, TRNG, random number generator, true, silicon, IP, safenet, security, macsec, ipsec, crypto, random, FIPS, SP800-90A/B/C, DRBG | 1 | 1 | |
| Silicon IP | Security | TRNG | True Random Number Generator | TRNG-IP-77 | Rambus Fast TRNG, SP800-90A/B/C, with DRBG | RNG, TRNG, random number generator, true, silicon, IP, safenet, security, macsec, ipsec, crypto, random, FIPS, SP800-90A/B/C, DRBG | 1 | 1 | |
| Chips | Memory Interface | DDR5 | Temperature Sensor | TS5110-G1B | Rambus DDR5 Temperature Sensor | DDR5, RDIMM, RCD | https://go.rambus.com/ddr5-temperature-sensor-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Power Management IC for Servers | P1945XXGA1 | PMIC5000 High Current Power Management IC for Servers | DDR5, RDIMM, PMIC, Power Management IC | https://go.rambus.com/ddr5-server-pmics-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Power Management IC for Servers | P1943XXGA0 | PMIC5010 Low Current Power Management IC for Servers | DDR5, RDIMM, PMIC, Power Management IC | https://go.rambus.com/ddr5-server-pmics-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Chips | Memory Interface | DDR5 | Power Management IC for Servers | P1947XXGA1 | PMIC5020 Extreme Current Power Management IC for Servers | DDR5, RDIMM, MCR DIMM, PMIC, Power Management IC | https://go.rambus.com/ddr5-server-pmics-product-brief, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, https://www.rambus.com/wp-content/uploads/2019/09/document-outline.svg, document icon | ||
| Silicon IP | Interconnect | PCIe | Controller | vDMA | Rambus Many-Channel Centralized DMA Controller with AMBA AXI Interface | DMA Engine, DMA, PCIe, PCI Express, FPGA, Altera, Xilinx, DMA AXI | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Decoder | VESA DSC Decoder for AMD FPGAs | Rambus VESA DSC Decoder for AMD FPGAs | VESA, DSC, Decoder, AMD, Xilinx, FPGA, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Decoder | VESA DSC Decoder for ASIC | Rambus VESA DSC Decoder for ASICs | VESA, DSC, Decoder, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Decoder | VESA DSC Decoder for Intel FPGAs | Rambus VESA DSC Decoder for Intel FPGAs | VESA, DSC, Decoder, Intel, Altera, FPGA, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Encoder | VESA DSC Encoder for AMD FPGAs | Rambus VESA DSC Encoder for AMD FPGAs | VESA, DSC, Encoder, AMD, Xilinx, FPGA, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Encoder | VESA DSC Encoder for ASIC | Rambus VESA DSC Encoder for ASICs | VESA, DSC, Encoder, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Encoder | VESA DSC Encoder for ASIC (ASIL-B) | Rambus VESA DSC Encoder for ASIC for Automotive, ASIL-B | VESA, DSC, Encoder, ASIL-B, video compression | 1 | | |
| Silicon IP | Video Compression | VESA DSC | Encoder | VESA DSC Encoder for Intel FPGAs | Rambus VESA DSC Encoder for Intel FPGAs | VESA, DSC, Encoder, Intel, Altera, FPGA, video compression | 1 | | |
| Silicon IP | Video Compression | VESA VDC-M | Decoder | VESA VDC-M Decoder for ASIC | Rambus VESA VDC-M Decoder for ASICs | VESA, VDC-M, Decoder, video compression | 1 | | |
| Silicon IP | Video Compression | VESA VDC-M | Encoder | VESA VDC-M Encoder for AMD FPGAs | Rambus VESA VDC-M Encoder for AMD FPGAs | VESA, VDC-M, Encoder, AMD, Xilinx, FPGA, video compression | 1 | | |
| Silicon IP | Video Compression | VESA VDC-M | Encoder | VESA VDC-M Encoder for ASIC | Rambus VESA VDC-M Encoder for ASICs | VESA, VDC-M, Encoder, video compression | 1 | | |
| Silicon IP | Video Compression | VESA VDC-M | Encoder | VESA VDC-M Encoder for Intel FPGAs | Rambus VESA VDC-M Encoder for Intel FPGAs | VESA, VDC-M, Encoder, Intel, Altera, FPGA, video compression | 1 | | |
| Silicon IP | Security | WHIRLPOOL | Cipher Accelerator | WHIRLPOOL-IP-51 | Rambus Whirlpool Cryptographic Accelerator Core | Rambus DPA Resistant Core Whirlpool | 1 | 1 | |
| Silicon IP | Interconnect | PCIe / CXL | Add-on Core | XpressAGENT | Rambus XpressAGENT Add-on Module | PCIe, CXL, PCI Express, Compute Express Link, Debug | 1 | 1 | |
| Silicon IP | Security | ZUC | Cipher Accelerator | ZUC-IP-48 | Rambus 3GPP ZUC Engine | 3GPP, 128-EEA3, 128-EIA3, ETSI/SAGE, hashing, silicon, SoC, authentication, security | 1 | 1 |
From the blog
News
Rambus Safeguards Accelerated Computing with FPGA-targeted Security IP
Highlights:
- Bring FPGAs with a state-of-the-art offering of security IP products
- Secures the broad range of FPGAs from high-performance accelerators to low-power, lightweight devices
- Supports FPGAs serving applications for the Data Center, Artificial Intelligence / Machine Learning, Edge, IoT, Defense, and more
SAN JOSE, Calif. – Aug. 22, 2023 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced a full suite of Security IP solutions for the FPGA market with state-of-the-art cryptographic, side-channel, and Quantum Safe protections. Designed to meet the unique needs of FPGAs, the offering secures the broad range of devices from high-performance accelerators for generative AI, to low-power solutions for IoT devices. Rambus security IP protects FPGAs serving applications in the Data Center, AI/ML, Edge, IoT, Defense, and beyond.
“As customer demand for security continues to accelerate, Rambus is dedicated to providing state-of-the-art security IP for the broad range of applications increasingly enabled by FPGAs,” said Neeraj Paliwal, general manager of Security IP at Rambus. “Our security IP solutions safeguard these FPGA devices now and in the future with Quantum Safe protection from PQC attacks.”
“In the increasingly distributed and accelerator-based computing architectures enabled by Intel FPGAs, it is mission critical to secure data and devices against today’s threats and those that arise with the advent of quantum computing,” said Premal Buch, vice president and general manager of Programmable Solutions at Intel. “We’re pleased to see Rambus offer security IP solutions tailored to FPGAs powering the growing landscape of accelerated computing.”
As part of the industry-leading portfolio, Rambus offers advanced FPGA targeted security IP products including root of trust, 800G MACsec, IPsec, classic and quantum safe public key encryption solutions. Leveraging pioneering work in differential power analysis (DPA) and fault injection attack (FIA) countermeasures, Rambus security IP delivers the highest levels of protection available against both cryptographic and side-channel attacks. With new Quantum Safe security IP products, Rambus futureproofs the protection of FPGAs for the coming Post Quantum Cryptography (PQC) era.
For more information about Rambus Security IP, please visit www.rambus.com/security.
RT-66x Programmable Root of Trust
The Rambus RT-66x Root of Trust IP are fully programmable, FIPS 140-3 compliant (or certified for the RT-660F) hardware security anti-tamper cores offering security by design for data center and other highly-secure applications. The RT-660 protects against a wide range of hardware and software attacks with state-of-the-art anti-tamper security techniques. The RT-660 is a security co-processor, built on a custom-designed 32-bit RISC-V architecture, along with dedicated secure memories.
The RT-660 offers superior anti-tamper attack protection through the implementation of Differential Power Analysis (DPA) countermeasures and state-of-the-art fault injection attack (FIA) protections. The RT-660 implements DPA and FIA protected AES, RSA, and ECC cryptographic accelerator cores. The RT-660 provides hardware implementations of a NIST SP800-90a/b/c compliant TRNG (true random number generator), Public Key Engine (RSA up to 8192 bits and ECC up to 521 bits), AES (all modes), HMAC and SHA-2/-3 crypto accelerators.
The RT-661 adds the OSCCA SM2/3/4 Chinese cryptographic accelerators. The RT-664 takes the robust feature set of the RT-660 and adds a Quantum Safe Engine with FIPS 203 ML-KEM (CRYSTALS-Kyber) and FIPS 204 ML-DSA (CRYSTALS-Dilithium), as well as XMSS and LMS stateful hash acceleration, to safeguard against quantum computer attacks.
The RT-66x IP are the ideal choice for chip and system architects designing FPGA and ASIC solutions for applications requiring the highest level of security.
Security CertificationsRT-600 Root of Trust Series A New Generation of Security Anchored in Hardware
This latest generation of the Rambus RT-600 Root of Trust IP offers many new features designed to support the security needs of customers today and into the future. These features include Quantum Safe Cryptography, Caliptra Root of Trust for Measurement (RoTM) emulation, an embedded physical unclonable function (PUF), as well as many architectural improvements, such as larger memory space and 64-bit addressing support.
How the Root of Trust Works
While built upon a RISC-V architecture, the RT-660 RISC-V CPU is a custom implementation designed specifically for security use cases. Rambus employed over 20 years of device security experience to build a security co-processor providing the highest levels of siloed and layered security. The RT-660 is designed for integration into government ASICs and FPGAs, offering secure execution of authenticated user applications, tamper detection and protection, and secure storage and handling of keys and security assets.
The Root of Trust offers a siloed approach to security. While located on the same silicon as the main processor, the secure processing core is physically separated. A layered security approach enforces access to crypto modules, memory ranges, I/O pins, and other resources, and assures critical keys are available through hardware only with no access by software. The Rambus Root of Trust RT-660 supports all commonly deployed host SoC processor architectures, including ARM, RISC-V, x86 and others.
The Rambus Root of Trust supports multi-tenant deployments by offering true multiple root of trust capabilities. Each individual Secure Application can be assigned its own unique keys, meaning permissions and access levels are set completely independent of others. Secure Applications are siloed from each other, ensuring the best approach to security. OEMs can determine access levels and permissions for each and all processes operating within the secure processor.
Dedicated FPGA Configuration
The RT-660 is available in an FPGA configuration for synthesis in programmable logic. This configuration is designed to map optimally (for maximum utilization and frequency) into an FPGA fabric and connect either to on-board or external CPUs. In addition, the RT-660 is expanded with an additional OTP emulation model to overcome the lack of (or limitation of) true nonvolatile one-time programmable memory in certain FPGA families. This module allows storing secure assets in external flash in a secure way.
Secure Applications
Included with the RT-66x Hardware Root of Trust IP are a series of standard secure applications (“containers”) to speed development, including secure boot, identity management, HSM reference, and others. A container development kit (CSDK) is also included to allow the development of custom containers for specific use cases.
Rambus can optionally offer dedicated FIPS 140-3 support packages to its licensees that provide FIPS 140-3 related certification documentation, FIPS test scripts, and dedicated FIPS support.
Deep Anti-Tamper Experience
As the inventor and pioneer of DPA and an acknowledged leader in device security, Rambus is uniquely qualified to provide anti-tamper solutions for the most stringent requirements. Rambus technologies protect more than 9 billion chips per year, and as a US-based, independent company, Rambus has the experience and pedigree to be the solution provider of choice. Rambus has for more than 20 years supplied solutions for government and defense applications, including anti-tamper cores, software libraries, and testing workstations.
Protecting Data and Devices Now and in the Quantum Computing Era
Quantum computing is being pursued across industry, government and academia with tremendous energy and is set to become a reality in the not-so-distant future. Once sufficiently large quantum computers exist, traditional asymmetric cryptographic methods for key exchange and digital signatures will be broken. Many initiatives have been launched throughout the world to develop and deploy new quantum-resistant cryptographic algorithms, known as Post-Quantum Cryptography (PQC).
Solution Offerings
Features
Deliverables
Features
Superior Security
- Hardware Root of Trust employing a custom 32-bit RISC-V processor
- Multi-layered security model provides protection of all components in the core
- NIST CAVP and CMVP compliant for FIPS 140-3 validation
- FIPS 140-3 CMVP Level 2 certified (RT-660F)
- State-of-the-art anti tamper techniques
- DPA-resistant cryptographic accelerators
- FIA-protected cryptographic accelerators
- Caliptra* Root of Trust for Measurement with DICE and X.509 support option
- TRNG and PUF entropy sources
- Quantum Safe Engine (QSE)
- Secure lifecycle management
- Secure provisioning with Rambus CryptoManager Root Server (CMRS)
* This is an unofficial implementation of the Caliptra specification. It is not Caliptra certified.
Enhanced Flexibility
- 3rd-party applications run securely within trusted boundary, each with its own assigned security permissions
- Complete development environment allows OEMs and users to easily develop secure applications (”containers”); standard use case application containers provided
- Support for secure provisioning of keys and firmware at manufacturing or in the field
- Support for multiple roots of trust within a single secure core
- Secure applications can be assigned unique keys, allowing independent permissions and access levels
Security Models
- Hierarchical privilege
- Secure key management policy
- Hardware-enforced isolation/access control/protection
- Error management policy
Cryptographic Accelerators
- RT-660F: NIST CMVP certified. NIST CAVP hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2/3 (all modes), RSA up to 4096 or 8192 bits, ECC up to 521 bits, and a SP800-90A/B Certified TRNG
- RT-660: As per RT-660F + LMS and XMSS hash-based signature schemes, SHAKE XOF, NIST CMVP compliant signature schemes, and SHAKE XOF
- RT-661: As per RT-660 + Chinese Encryption with OSCCA SM2/3/4
- RT-662 As per RT-660 + IoT Encryption with ChaCha20/Poly1305
- RT-664: As per RT-660 + Quantum Safe Engine with ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium)
Security Modules
- Canary logic for protection against glitching and overclocking
- Secure key derivation and key transport
- Life cycle management
- Secure test and debug
- Feature management
Deliverables
Complete Documentation
- Integration guides
- Reference manuals
- Programming guides
RTL and FW Package
- Verilog RTL for synthesis and simulation
- Standard EDA tool flow scripts and support files
- Verification test bench and test vectors
- Boot loaders and secure RTOS and security monitor firmware
- HLOS APIs for accessing RT-66x capabilities
SW SDK Package
- SDK including the development environment, complete emulation with debugging capabilities of the RISC-V and crypto cores on QEMU
- One-step install emulation with multiple samples and reference code to help customers kickstart their secure application development
FIPS 140-3 Support Package (Optional)
- FIPS 140-3 test scripts
- FIPS 140-3 related certification documentation
- FIPS 140-3 support
Secure Applications
| Secure Application | Description |
|---|---|
| Linux Secure Boot | Implements secure boot for Linux OS, secured by the Root of Trust co-processor |
| Linux Secure FOTA | Implements secure Firmware Over the Air (FOTA) updates for Linux OS |
| Secure Boot | Uses the Root of Trust co-processor to assist in the secure boot process of ASICs and FPGAs |
| Secure Data Storage | Uses the Root of Trust co-processor to protect user credentials or biometric templates |
| Open SSL Hardening | Hardens the OpenSSL crypto operations via the Root of Trust secure co-processor |
| Reference HSM | Implements a basic HSM supporting AES, HMAC, SHA256, ECDSA, X.509 certificates and secure storage |
| Unique ID Generator | Creates a Root of Trust unique ID and stores it in the Root of Trust NVM (Non Volatile Memory) |
