Rambus

At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.

Chip + Interface IP Glossary

A glossary of Chip and Interface IP terminology and relevant solutions.

A

ASIC (Application-Specific Integrated Circuit)
AXI (Advanced eXtensible Interface)

B

Bank Management
Bank Refresh

C

Clamshell Mode
Controller
Crosslink
Camera Serial Interface (CSI-2)

D

Data Bus Inversion

H

Hash-based Message Authentication Code (HMAC)
Hardware Security Module (HSM)
Hierarchical Signature System (HSS)
Hardware Security (HWSEC)

I

Identity-Based Systems (IBS)
Inline Cipher Engine (ICE)
Integrity and Data Encryption (IDE)
Integrated Hardware Security Module (IHSM)
Inline Memory Encryption (IME)
INDistinguishability under Chosen Ciphertext Attack (IND-CCA)
INDistinguishability under (adaptive) Chosen Plaintext Attack (IND-CPA)
Internet Protocol Security (IPsec)

K

Key Derivation Function (KDF)
KYBER
Key Wrap with Padding (KW(P))

L

Leighton-Micali Signature Scheme (LMS)
Leighton-Micali One-Time Signature (LMOTS)
Long Term Stable (LTS)

M

Media Access Control Security (MACsec)
Module-Lattice based Digital Signature Algorithm (ML-DSA)
Module-Lattice based Key Encapsulation Mechanism (ML-KEM)
Memory Management Unit (MMU)
Magnetic Random Access Memory (MRAM)

N

National Institute of Standards and Technology (NIST))
Non-deterministic Random Bit Generator (NRBG)
Non-Volatile Memory (NVM)

O

Output Feedback (OFB)
On Demand CMRT Configuration (ODM)
Office of the State Commercial Cryptographic Administration (OSCCA)
One Time Programmable (OTP)

P

Personalization Container for CMRT (Perso)
Personalization
Public Key Infrastructure/Accelerator/Engine (PKI/A/E)
Power Management Unit (PMU)
Proof of Concept (PoC)
Power on Reset (POR)
Post-Quantum Crypto (PQC)
Private Key
Provisioning
Arm Platform Security Architecture (PSA)
Public Key
Physically Unclonable Function (PUF)

Q

Quick Emulator (QEMU)
Quantum Safe Cryptography (QSC)
Quantum Safe Engine (QSE)

R

Random Bit Generator (RBG)
Read Only Memory (ROM)
Root of Trust (RoT)
Rivest Shamir Adleman (RSA)
Register Transfer Level (RTL)
RV32ICM

S

Second Stage Boot (Sboot)
Side Channel Attack (SCA)
Software Development Kit (SDK)
Secure Boot
Global Platform Security Evaluation Standard for IoT Platforms (SESIP)
Secure Hash Algorithm (SHA)
Secure Hash Algorithm Keccak (SHAKE)
Secure Hardware Extension (SHE, SHE+)
Synthetic IV (SIV)
Stock Keeping Unit (SKU)
SM2
SM3
SM4
System on Chip (SoC)
Sea of Gates (SoG)
Safety of the Intended Functionality (SOTIF)
Secure Socket Layer (SSL)
Symmetric Key

T

Transaction Level Model (TLM)
Transport Layer Security (TLS)
Trusted Platform Module (TPM)
True Random Number Generator (TRNG)
Test Vector Leakage Assessment (TVLA)

U

Universal Verification Methodology (UVM)

V

Virtual Command Queue

X

XOR-Encrypt-XOR (XEX)
Extended Merkle Signature Scheme (XMSS)

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