2Tbps multi-lane HBM2 PHY
Earlier this month, GLOBALFOUNDRIES demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs).
The 2.5D ASIC solution includes a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus. Building on the 14nm FinFET demonstration, the solution will be integrated on the company’s next-generation FX-7™ ASIC design system built on GF’s 7nm FinFET process technology.
Overcoming technical challenges
As Dave Lammers of the GLOBALFOUNDRIES Foundry Files Blog reports, development of the PHY presented a “technical challenge” that Rambus engineers helped tackle along with the GF team.
“The HBM2 PHY is a mixed signal function that must be designed very specifically to each process node. [So], we [did extensive] modeling of the channel and then designed the PHY to meet those channel requirements,” Frank Ferro, senior director of product marketing at Rambus, told the Foundry Files Blog. “[This] was a collaboration. We had long conference calls to [discuss] the whole process. But from day one, it worked, and that is a strong testament to the Rambus (modeling and signal integrity) tools and the engineers who have a history of designing these PHYs.”
“The largest core we’ve produced for an ASIC”
Tad Wilder, a principal member of the technical staff at GF, told the Foundry Files that the two terabits-per-second of bandwidth is quite an impressive amount of bandwidth for a single core.
“With the ability to place up to four HBM2 PHYs on a chip, this gives ASIC designers an unprecedented eight terabits-per-second of low power, low latency DRAM access to work with,” he stated.
Wilder also confirmed that the 14nm HBM PHY “is the largest core we’ve produced for an ASIC,” with 15,000 internal pins talking to the memory controller and 1,700 external pins talking to the base die of the DRAM stack across the interposer.
Each DRAM stack contains a base die, says Wilder, which communicates with the ASIC’s HBM2 PHY and up to eight stacked DRAM die above, through thousands of vertical Through Silicon Vias (TSVs). The total memory per HBM DRAM stack is up to 32GB. To mitigate the noise of more than 1,000 I/O possibly switching, the ASIC HBM2 PHY can take advantage of the complete independence of the eight 128 bit channels by skewing the timing of each channel with respect to another.
Besides the 1,700 pins between the PHY and the HBM2 DRAM, Wilder told Foundry Files that the technology supports roughly 15,000 on-chip I/Os to connect the logic circuits on the ASIC. In addition, he says, there are eight HBM2 channels of 128 bits each, while each HBM2 DRAM includes four stacked die that are connected by thousands of vertical through-silicon-vias (TSVs). The PHY communicates with the base die, which talks to the three dies above it.
The future of HBM2 & 2.5D solutions
According to Linley Group analyst Bob Wheeler, momentum is building for the HBM2 standard.
“Networking customers saw the very wide bandwidth, saw that it was closer to the CPU, and pretty quickly moved to the HBM2 standard,” Wheeler told the Foundry Files. “On a single interposer you can do a lot more interfaces. It is a solution for those applications where you don’t want to go out and drive signals across the DIMM.”
With regards to the future of 2.5D solutions, Dave McCann, vice president of packaging R&D and business technical operations at GF, noted that the industry started working on 2.5D about five years ago, with some products brought to market for leading-edge graphics. Now, says McCann, the second adopter is networking.
Asked if he thought 2.5D solutions would proliferate, McCann said “it is a really great technology that has come of age, with significant revenues. The question is: can we drive down the cost to get it to the next level of volume?”
Rambus’ Frank Ferro expressed similar sentiments. As Ferro notes, the spread of 2.5D solutions in the high-performance part of the industry is contingent upon manufacturing yields and bringing down the cost of HBM2 DRAM.
“2.5D needs to be proven out with high-volume manufacturing. It is a fairly big piece of silicon and you have to really control warpage,” he added.