Writing for PC Magazine, Michael J. Miller notes that although most of the discussion around Moore’s Law has thus far focused on logic chips, the memory industry has clearly entered a transitional stage.
“DRAM shrinks have slowed dramatically. Most of the makers are now in the transition to 20nm DRAM with perhaps one or two more generation left to go,” Miller explained.
“Any further advances in density or cost will then have to come from additional manufacturing capacity, larger wafer sizes (450mm), 3D chip stacking (Hybrid Memory Cubes), or perhaps eventually a new type of memory altogether such as MRAM.”
Commenting on the above, Loren Shalinsky, a Strategic Development Director at Rambus, told us that despite a certain amount of industry consternation, Moore’s Law is certainly still alive.
“As Miller himself points out, ‘the reports of the Law’s death have been greatly exaggerated,’” he said. “To be sure, while the transition time from node to node shifts over time, it’s really no different than Moore’s original observation, which shifted from 1 year to 2 years. Plus, specific semiconductor verticals have always progressed at their own individual cadence.”
According to Shalinsky, one large flash vendor was once capable of doubling the storage capacity on flash for nearly 5 years in a row.
“This was accomplished via a combination of quick full node transitions and the introduction of MLC – storing 2 bits of data in a single memory cell,” he continued.
While this feat of doubling storage capacity so quickly is unlikely to be repeated, it does indicate that different technologies can go through rapid transition phases.
“3D NAND maintains the tradition of more transistors per die (area), by pushing a lever other than node size by stacking transistors on top of each other. This hails back to the original concept of Moore’s Law: the number of transistors doubling in a given time frame.”
Indeed, as Miller explains, 3D NAND uses multiple layers of memory cells fabricated with very thin, uniform films. Simply put, this means the feature sizes of the individual cells no longer need to be so small, although the density continues to scale – potentially to 1 terabit on a chip – by adding more layers.
“At Semicon West, the equipment companies said the transition to 3D NAND is happening more quickly than expected, and by some estimates, 15 percent of the world’s capacity by bits will have shifted by the end of this year,” he concluded.