Semiconductor Engineering editor in chief Ed Sperling recently reported that the current emphasis on lowering power – in everything from wearable electronics to data centers – is turning into a “perfect storm” for the semiconductor ecosystem.
“In the past, most issues involving power—notably current leakage, physical effects such as electromigration, electrostatic discharge, RC delay and reduced battery life from inefficient designs—were dealt with by large, sophisticated engineering teams at leading-edge process nodes,” Sperling explained.
“When they couldn’t solve those problems the foundries stepped in and adjusted their processes. But with 55nm now considered a mainstream process for the Internet of Things, and most designs now using multiple cores and power domains—sometimes as many as 100 power domains per design—everyone is being forced to grapple with incredibly complex power techniques.”
To make matters worse, says Sperling, the manufacturing side is already dealing with its own power-related problems, which includes shrinking gate oxides between ever-thinner wires, increasing dynamic power density at 16/14nm and beyond, as well as a massive industry effort to create next-generation processes capable of handling increasingly complex designs.
According to Steven Woo, VP of enterprise solutions technology at Rambus, one particular issue that continues to grow in importance is power integrity.
“A good analogy is what happens if you turn on all the water inside a building,” Woo told Semiconductor Engineering. “You lose pressure everywhere. For a chip, if you turn on every subsystems, that’s devastating. You may not have enough voltage to turn on everything, and power integrity goes down.”
Not surprisingly, power-related security concerns may also prompt a reassessment of how future chips and electronics are designed.
“Security requires power to operate, but the flip side is that power is noisy. When you activate circuits you can monitor that noise,” he added. “There’s a growing problem with differential power analysis. What it really comes down to is that you’re trying to give confidence for some period of time, so now you have to determine what is a useful lifetime and how long you’re going to guard it.”
As we’ve previously discussed on Rambus Press, physical electronic systems routinely leak information about the internal process of computing. In practical terms, this means attackers can exploit various side-channel techniques to gather data and extract secret cryptographic keys.
As such, the Rambus Cryptography Research division has designed a range of DPA countermeasures that offer a combination of software, hardware and protocol techniques specifically designed to protect tamper-resistant devices from side-channel attacks. These include leak reduction, incorporating randomness, generating amplitude and temporal noise, as well as executing protocol-level countermeasures.
Interested in learning more about how Rambus is helping to secure SoCs, devices and content? You can read more about our DPA countermeasures here, CryptoFireWall Cores here and CryptoManager platform here.