Globalfoundries – which operates a total of 8 semiconductor fabrication facilities across the globe – has a long history of collaborating with Rambus on a wide variety of projects.
In 2011, the two industry heavyweights began working closely together on the foundry’s 28-nanometer super low power (28nm-SLP) process, with Globalfoundries’ assembly support team also providing wirebond and flipchip packaging options on high-speed PHY designs.
Two separate memory architecture-based 28nm silicon test chips were subsequently announced in July 2012. The first piece of silicon targeted smartphones and tablets, while the latter was designated for servers, or compute main memory applications.
As Sunil Bhardwaj, a director of strategic partnerships at Rambus points out, new chip starts and IP enablement are becoming infinitely more complex.
“The cost of productizing process technology, new chip implementation, advanced EDA tools and a comprehensive IP portfolio is now a prohibitively expensive endeavor,” Bhardwaj told Rambus Press.
“In addition, demand for faster time to market, lower cost, and reduced power consumption, has increased concurrently. This is why it is critical for ecosystem companies to collaborate on reducing overhead, as well as to continuously scale and demonstrate technology to ensure a low-risk, rapid industry adoption.”
As we noted previously, Rambus and Globalfoundries have worked together in such a manner by demonstrating the capabilities of 28nm, advanced foundry processes and Rambus R+ design innovations.
“We complement each other’s offerings, all while highlighting the production readiness of the design enablement ecosystem of both Globalfoundries’ foundry and Rambus IP customers,” Bhardwaj explained.
“For example, R+ IP products benefit from Globalfoundries’ design enablement support and expertise, including process design kits (PDKs), DFM kits, analog mixed signal reference flow, extensive implementation services and silicon proven logic libraries.”
Most recently, says Rambus exec Joe Gullo, the two companies have collaborated on both low-power and high performance designs, with silicon demos (in progress) of low-power memory PHYs targeting industry standard, as well as beyond data-rates and multi-protocol high speed serial links.
“The divergent power performance requirements from these separate IP product families highlight the comprehensiveness of the 28nm foundry platform,” he added.
“We look forward to collaborating with the industry and Globalfoundries to scale and productize these IP platforms to 14nm and beyond.”
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