The evolution of server DIMM chipsets in the data center
This entry was posted on Tuesday, October 31st, 2017.
Victor Cai, a director of product marketing at Rambus, recently wrote an article for Semiconductor Engineering that explores the evolution of server DIMM chipsets in the data center.
According to Cai, DDR3 server DIMM chipsets running at 800 Mbps first hit the market in 2006 and started to ramp in 2007. 7 years later, DDR4 server DIMM chipsets running at 2133 began shipping. Concurrently, DDR3 server DIMM chipsets spanned the following five speeds in 2014: 800, 1066, 1333, 1600 and 1866.
“In the last years, DDR4 buffer chipset shipments have crossed over in term of volume, with DDR4 chipset speeds expected to reach 3200 by 2018 or 2019,” Cai explains. “In addition to increased bandwidth and density, DDR4 buffer chips offer data centers the critical benefits of advanced signal equalization.”
As an example, says Cai, Rambus registered clock driver (RCD) and data buffer (DB) chips are equipped with sophisticated decision feedback equalizers (DFEs) which are typically used in the communication industry for 10G or higher SerDes.
“Essentially, DFE circuits allow RCDs and DBs to operate with greater margin on typical systems – as well as in challenging environments where older chipsets are prone to malfunction or fail to achieve higher speeds,” states Cai. “Equipping both chips (RCD and DB) with DFE capabilities allows the DIMM chipset to push the limits of both the command address bus as well as the DQ bus.”
Moreover, says Cai, DFE circuits enable DIMMs to run at speeds of 3200, exceeding original industry expectations for this generation of buffer chips. However, signal integrity challenges are becoming more prevalent as bandwidth, density and speeds increase.
“Fortunately, lessons learned from other markets (such as communications) will merge with DDR technology to help push the single-ended bus to its limit,” he notes.
With regards to current DIMM chipset deployment, Cai observes that DDR4 buffer chipset shipments are ramping up as the price of DDR4 silicon continues to decrease. This, says Cai, is because data centers only upgrade their memory subsystems when the economics of performance per dollar meets a certain threshold.
“For most data centers, this means a transition from DDR3 to DDR4 within the DDR4-2400 generation – as price parity is reached between DDR3 DRAM and DDR4 DRAM,” he elaborates. “Many industry heavyweights have already transitioned or are in the process of switching over to DDR4 as their primary server memory type. Looking towards the near future, speed increases and price reductions will further accelerate adoption of DDR4 server DIMM chipsets by data center customers.”
In conclusion, says Cai, memory buffer chips continue to steadily evolve, as is illustrated by the number of technical advances (such as DFE) seen from one generation of silicon to the next.
“The importance of server DIMM chipsets will only continue to increase, as the industry attempts to sustain Moore’s Law and maximize the limitations of Von Neumann architecture in a changing data center,” he adds.