Benjamin Jun’s presentation at the Developers Track of the 2005 RSA Conference.
Download “Ten Bugs That Cost Our Customers Billions – RSA 2005”
Benjamin Jun’s presentation at the Developers Track of the 2005 RSA Conference.
Download “Ten Bugs That Cost Our Customers Billions – RSA 2005”
Los Altos, California, United States
– 08/23/2005
Who: Rambus Inc. (Nasdaq:RMBS)
Where: Intel Developer Forum
Booth # 609
Moscone Convention Center West
San Francisco, CA. USA
When: August 23 – 25, 2005
At IDF, Rambus will showcase a number of its high-speed chip interface solutions, including its DDR2 PHY designs and its XDR™ memory interface solution with data rates ranging from 3.2-8.0 GHz.
In addition, Rambus and its partners will demonstrate and display its serial link interface products in key application areas:
Rambus’ integrated PCI Express solution, incorporating both digital controller and PHY technologies, will also be on display, demonstrating how an integrated solution can help reduce third-party vendor IP issues and speed time to market.
Rambus will also show its PCI Express PHYs passing the PCI Express Base 1.1 electrical compliance tests using the Tektronix TDS6154C Digital Storage Oscilloscope with RTEye™ PCI Express compliance test software.
* PCI Express is a trademark of PCI-SIG. Brands, product names and marks are trademarks, registered trademarks, or trade names of their respective owners.
Advanced XDR memory to enable disruptive enterprise and consumer computing models
Los Altos, California, United States – 08/22/2005
Rambus Inc. (Nasdaq:RMBS), one of the world’s premier technology licensing companies specializing in high-speed chip interfaces, today announced that fabless semiconductor company Teradici Corporation has signed a license agreement for Rambus’ XDR memory controller interface cell, dubbed XIO. As part of the agreement, Rambus will also provide the logic layer of the memory controller, the XMC. This agreement enables Teradici to develop an advanced, high performance solution for the next generation of enterprise and consumer computing.
“Teradici is developing a complex, high-speed chip design that requires the most advanced memory technology available today,” said Dan Cordingley, CEO at Teradici Corporation. “The combination of Teradici’s unique graphics algorithms and deep talent for integrated chip design, coupled with Rambus’ expertise in high-speed signaling, will enable us to provide a new approach for personal computing in the future. We look forward to a long and successful relationship with the Rambus engineering teams.”
The Rambus XIO cell is a high-performance, low-latency controller interface to XDR DRAM memory sub-systems, allowing up to 8 gigabytes-per-second of bandwidth in a 16-bit wide interface from a single memory device. It is a versatile CMOS macro cell that can be seamlessly integrated into a wide variety of target processes. The general purpose cell is independent of the logical memory controller design, enabling support for a wide variety of memory applications needing high bandwidth and low latency. The XIO provides a wide, on-chip, CMOS-level signaling interface to the memory controller logic and a narrow, high-speed Differential Rambus Signaling Level (DRSL) interface to the external XDR memory system.
“Working on advanced, innovative programs such as Teradici’s allows us to showcase our memory system architectures to new and interesting platforms,” said Laura Stark, vice president of Platform Solutions at Rambus. “Our engineering teams are focused on designing and developing the most advanced interface designs that help our customers meet the ever-increasing demands of the market.”
For additional information on all the Rambus interface products, please go to
www.rambus.com/products.
Industry-leading integrated controller and PHY deliver superior results in broad range of applications
[Update] Read our primer: Rambus launched PCI Express 5 »
Los Altos, California, United States – 08/08/2005
Rambus Inc. (Nasdaq:RMBS), one of the world’s premier technology licensing companies specializing in high-speed chip interfaces, today announced the availability of its fully integrated PCI Express* solution. This complete solution consists of silicon-proven digital controllers and PHY cells meeting the PCI Express 1.1 base specification. Supported by a PCI Express evaluation kit, the Rambus integrated solution is ideal for customers searching for end-to-end implementation and validation, which eliminates the interoperability risks and complexities associated with multi-vendor IP.
Rambus’s PCI Express solution includes vertically integrated testing features to help customers facilitate system bring-up and debug for improved production test coverage. The Rambus solution allows design optimizations to be made across the PHY and logic layers to result in lower power, area and latency for cost- and performance-sensitive applications.
“Our complete solution with both the digital controller and PHY ensures our customers can get their products to market faster by reducing integration and validation risks as well as providing value-added features that go beyond the current specifications,” said Laura Stark, vice president of the Platform Solutions Group at Rambus. “Designers are concerned about getting their PCI Express implementation to work the first time. With our solution they have a reliable, fully verified and interoperability-tested solution that greatly reduces the risk of integrating third-party IP.”
For a streamlined design-in experience, Rambus offers developers the PCI Express evaluation kit, a system level evaluation platform that supports:
Rambus PCI Express digital controllers are highly configurable, and are delivered with a complete test environment, test cases and synthesis environment for maximum ease of integration. Rambus PCI Express PHY cells are available on multiple foundry and captive processes at process nodes ranging from 180nm to 65nm. Numerous Rambus customers are in production in high-volume applications such as graphics, chipsets, storage, and communications ICs.
Rambus has also demonstrated its Turbo PCI Express platform with serial links operating at 5.0Gbps and 6.25Gbps data rates to meet future PCI Express requirements. The Rambus PCI Express solution is represented with multiple entries on the PCI-SIG Integrators List, having passed compliance and interoperability testing by Rambus customers and partners. For more information on Rambus’s complete PCI Express offering, visit www.rambus.com/products/pciexpress.
Los Altos, California, United States – 08/04/2005
Rambus Inc. (Nasdaq:RMBS), one of the world’s premier technology licensing companies specializing in high-speed chip interfaces, today announced that Bob Eulau, Senior Vice President and Chief Financial Officer, will present a business overview at the Moors & Cabot Semiconductor conference on August 10, 2005 at 10:30 a.m. PT and B. Riley New York Investor Conference on August 11, 2005 at 8:10 a.m. PT.
This event will be available through a webcast and can be accessed at Rambus’s Investor Relations web site at https://investor.rambus.com/. The audio replay will be available on Rambus’s IR web site following the event.
Rambus is one of the world’s premier technology licensing companies specializing in the invention and design of high-speed chip interfaces. Since its founding in 1990, the company’s innovations, breakthrough technologies and integration expertise have helped industry-leading chip and system companies solve their most challenging and complex I/O problems and bring their products to market. Rambus’s interface solutions can be found in numerous computing, consumer, and communications products and applications. Rambus is headquartered in Los Altos, Calif., with regional offices in Bangalore, India, Chapel Hill, North Carolina, Taipei, Taiwan and Tokyo, Japan. Additional information is available at www.rambus.com.
ASICs used in market leading SANblade host bus adapters
Rambus Developer Forum, Tokyo, Japan – 07/08/2005
Rambus Inc. (Nasdaq:RMBS), one of the world’s premier technology licensing companies specializing in high-speed chip interfaces, today announced that QLogic Corporation (Nasdaq:QLGC), a storage area network (SAN) infrastructure company, has incorporated the Rambus PCI Express* digital controller core in their line of Fibre Channel storage processor ASICs. These ASICs are used in the popular QLogic SANblade line of Fibre Channel host bus adapters (HBAs), the year 2004 market share leader according to analyst firms Gartner, Dell’Oro and IDC.
“We chose the Rambus PCI Express end point core, because it was the most advanced core available on the market,” said Amit Vashi, senior director product marketing for QLogic Corporation. “Our engineers have given two thumbs up for the integration support that they received from the Rambus team.”
QLogic provides OEMs, resellers and system integrators with end-to-end SAN infrastructure solutions. The company produces the controller chips, host bus adapters, fabric switches and management software that are the backbone of storage networks for most Global 2000 corporations. QLogic serves customers with solutions based on all storage network technologies including SCSI, Internet SCSI (iSCSI), and Fibre Channel.
“The successful silicon implementation of our PCI Express digital controller is the result of Rambus’s rigorous design and verification processes and the extensive interoperability testing our team has performed with leading system platforms,” said Abhijit Sarid, group marketing manager for digital core products at Rambus. “This achievement underscores Rambus’s dedication to deliver products with the highest level of compatibility and reliability to ensure seamless integration into our customers’ designs.”
Rambus PCI Express digital controllers are highly configurable cores, available in end point, root complex, switch port, and hybrid (root complex and end point) configurations. The architecture is tailored to optimize link utilization, latency, power consumption and silicon footprint. The verilog cores are delivered with a complete test environment, test cases and synthesis environment for maximum ease of integration.
Rambus digital controllers are also available as part of a complete integrated PCI Express solution, which includes Rambus’s PCI Express PHY cells. The Rambus PCI Express PHY cells are available on multiple foundry and captive processes at process nodes ranging from 180nm to 65nm. Rambus’s PCI Express PHY cells are listed on the PCI-SIG Integrators List, having passed PCI-SIG compliance and interoperability testing by Rambus PHY cell customers and digital controller partners. The PCI-SIG is the special interest group that owns and manages PCI specifications as open industry standards. Rambus has also demonstrated its Turbo PCI Express platform with serial links operating at 5.0Gbps and 6.25Gbps data rates to meet future PCI Express requirements. For more information on Rambus’s broad PCI Express offering, visit www.rambus.com/products/pciexpress.
