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Home > Press Releases > Interface IP > Memory PHYs > HBM

HBM

Rambus and Northwest Logic Certify Interoperability of HBM2 Interface Solution for High-performance Networking and Data Center Applications

Integrated HBM2 PHY and Memory Controller provide validated, standards-compliant memory subsystem with superior signal integrity and reliability

SUNNYVALE, Calif. – Aug. 23, 2017 – Rambus Inc. (NASDAQ: RMBS), an innovator in semiconductor and IP products, today announced validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The solution builds on the growing ecosystem of Rambus partner products that interoperate with its latest HBM2 PHY IP core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets that require the maximum amount of bandwidth available through HBM2.

“Our work with Northwest Logic gives Rambus the functionality to provide a verified solution that reduces the engineering workload and time to market for chip designers” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “As Rambus extends its footprint in PHY support for leading-edge technologies, collaborative interoperability is essential for our end customers that demand early adoption. Memory interfaces are increasingly important in today’s new workloads, and the combination of Rambus HBM2 and Northwest Logic’ HBM2 Memory Controller core is a natural fit to support customer demands on both sides.”

The Northwest Logic HBM2 Memory Controller Cores are optimized for use in both ASICs and FPGAs, and support full-rate, half-rate and quarter-rate operations. The cores provide a solution that can be configured to exact customer requirements, are silicon-proven and are verified with the Rambus HBM2 PHY.

“Our HBM2 Memory Controller Core has been successfully deployed in a wide variety of customer systems demonstrating high reliability and performance,” said Brian Daellenbach, president of Northwest Logic. “We are excited to offer a complete HBM2 solution with Rambus ensuring our customers achieve the best possible combined memory solution for their high data demands.”

The Rambus HBM2 PHY and Northwest Logic HBM2 Memory Controller are each fully JEDEC compliant to the HBM2 standard, allowing the PHY and memory controller to interoperate. The Rambus HBM2 PHY is a high-performance memory IP core that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed, delivering higher efficiency and lower power consumption compared to other memory solutions on the market. For additional information on Rambus HBM2 PHY solutions, please visit https://www.rambus.com/memory-and-interfaces/ddrn-phys/hbm/

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About Rambus Memory and Interfaces Division 
The Rambus Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus products deliver improved time-to-market and first-time-right quality.

About Rambus Inc.
Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile payments, and smart ticketing. At Rambus, we are makers of better. For more information, visit rambus.com.

Rambus Introduces High Bandwidth Memory PHY on GLOBALFOUNDRIES FX-14™ ASIC Platform using 14nm LPP Process Technology

High-performance, power-efficient memory solution designed for today’s data centers

SUNNYVALE, Calif. – February 7, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced the availability of its High Bandwidth Memory (HBM) Gen2 PHY developed for GLOBALFOUNDRIES high-performance FX-14TM ASIC Platform. Built on the GLOBALFOUNDRIES 14nm FinFET (14LPP) process technology, the Rambus HBM PHY is aimed at networking and data center applications and designed for systems that require low latency and high bandwidth memory. This PHY is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, enabling a total bandwidth of 256 GB/s to meet the needs of today’s most data-intensive tasks.

“Data center needs are continuously changing and we are at the forefront of delivering memory interface technology designed to meet today’s most demanding workloads,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces division. “Through our collaboration with GLOBALFOUNDRIES, we are delivering a comprehensive and robust solution for high-performance data center and networking applications. Our HBM offering will allow data center solution developers to bring high performance memory closer to the CPU, thus reducing latency and improving the system throughput.”

“With the rise of cloud computing and the growing needs of Big Data, the computing power of data centers is burdened more than ever and hardware manufacturers are being called upon to deliver new solutions that can meet these challenges,” said Kevin O’Buckley, vice president product development GLOBALFOUNDRIES. “Working together with Rambus enables us to provide ASIC solutions to our customers with increased memory capacity and bandwidth, with improved power efficiency. This HBM innovation complements other advanced chip to chip interfaces in our ASIC platform, including our industry leading 56G Long Reach SerDes technology.”

The Rambus HBM PHY delivers high performance with lower power consumption when compared to other memory solutions. It combines 2.5D packaging with a wider interface (1024 bits) at a lower clock speed, which results in a higher overall throughput while remaining energy efficient for even the most high-performance computing applications. Rambus experts perform complete signal and power integrity analysis on the entire 2.5D systems to ensure all signal and thermal requirements are met.

The HBM PHY is another key component in Rambus’ memory and SerDes high-speed interface IP portfolio for networking and data center applications. For additional information on Rambus Memory and Interfaces solutions, please visit rambus.com/memory-and-interfaces.

Follow Rambus:
Company website: rambus.com
Rambus blog: rambusblog.com
Twitter: @rambusinc
LinkedIn: www.linkedin.com/company/rambus
Facebook: www.facebook.com/RambusInc 

Press contact:

Agnes Toan
Corporate Communications
(408) 462-8905
atoan@rambus.com

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