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Memory PHYs

Rambus Announces Tapeout of GDDR6 Memory PHY on TSMC 7nm Process Technology

Leading IP to support TSMC’s customers with AI, HPC, automotive and networking applications

SUNNYVALE and SANTA CLARA, Calif. – Jan. 30, 2019 – Rambus Inc. (NASDAQ: RMBS) today announced the tapeout of its GDDR6 PHY on TSMC 7nm FinFET process technology and is available from Rambus for licensing today. Leveraging almost 30 years of high-speed interface design expertise and using advanced process technology, Rambus has successfully taped out a GDDR6 PHY IP on TSMC 7nm process technology.  With ongoing engagements among design and verification customers, GDDR6 is applicable to a broad range of high-performance applications including networking, data center, advanced driver assistance systems (ADAS), machine learning and artificial intelligence (AI). This fastest discrete memory interface from Rambus will add to TSMC’s large portfolio of silicon proven intellectual property (IP), design tools and reference flows.

Expanding beyond traditional GPU and graphic applications, GDDR6 helps to address market needs in multiple, high-bandwidth applications, as memory performance becomes more critical for overall system performance. This latest addition to the Rambus high-speed-interface IP portfolio highlights the company’s leadership and long tradition of signal- and power-integrity expertise, remaining at the forefront of innovation in interface technology. By providing the industry’s highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques, GDDR6 offers system designers an alternative memory choice that is five times faster than traditional memory available today.

The Rambus GDDR6 offering will also add to TSMC’s portfolio of silicon-proven IP, via its Open Innovation Platform® (OIP) IP Alliance Program. In this program, TSMC’s IP and ecosystem partners like Rambus are able to tapeout and validate in silicon critical IP for TSMC’s various process nodes.

Benefits of the Rambus GDDR6 PHY:

  • Provides the industry’s highest speed of up to 16 Gbps, providing a maximum bandwidth of up to 512 Gbps.
  • Offers PCB and Package design support – allowing customers to quickly and reliably bring their high-speed designs to production.
  • Delivers a timing-closed hard macro solution for easy ASIC integration.
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximized signal and power integrity for devices and systems.
  • Presents a LabStation™ development environment that enables quick system bring-up, characterization and debug.
  • Supports high-performance applications including networking, data center, ADAS, machine learning and AI.

“By leveraging TSMC’s 7nm process technology, Rambus furthers its ability to offer first to market products and be on the leading edge of industry standards,” said Hemant Dhulla, VP and GM of IP Cores, Rambus. “We offer a complete system solution for integration, including PCB and package design, to help customers get to production faster. We’re excited to grow as a valuable ecosystem partner of TSMC and deliver a broad IP portfolio to maximize performance and flexibility for today’s most challenging systems.”

Availability
GDDR6 is available from Rambus today for licensing and integrating into system-on-chips (SoCs).

Demonstration Details at DesignCon 2019
At DesignCon from Jan. 29 – Jan. 31, 2019 in Santa Clara, California, Rambus will demonstrate a memory channel signaling at GDDR6 speeds. Rambus will also present, “Memory Options for High Performance Applications,” starting at 9:05 am PT on Jan. 30 in the room, “Great America 3,” that will discuss GDDR6 and other leading technologies. Visit Rambus at Booth 837 to learn more about GDDR6 applications.

For more information on our latest Rambus GDDR6 high speed memory offerings on TSMC, please visit https://www.rambus.com/gddr6.

Micron, Rambus, Northwest Logic and Avery Design to Deliver a Comprehensive GDDR6 Solution for Next-Generation Applications

BOISE, Idaho, Jan. 23, 2018 (GLOBE NEWSWIRE) — Micron Technology, Inc. (NASDAQ:MU), a leading memory and storage provider, today announced with Rambus Inc., Northwest Logic and Avery Design, their efforts to deliver a comprehensive solution for GDDR6, the world’s fastest discrete memory. This first-of-its-kind solution would enable GDDR6 use in advanced applications such as high-performance networking, autonomous vehicles, artificial intelligence and 5G infrastructure.

Prior generations of GDDR memories, enabled by GPU vendors, were focused exclusively on the graphics market. While this allowed graphics and game console designs to take advantage of the significant performance advantage offered by GDDR, other applications could not because the necessary building blocks were not available.

This comprehensive solution brings together the unique contributions of each company to solve that problem, extending the reach and benefit of GDDR6 well beyond its traditional graphics market. The solution would include:

Targeting up to 64GB/s, GDDR6 brings a significant improvement over the fastest available DDR4. This unprecedented level of single-chip performance, using proven, industry-standard BGA packaging provides designers a powerful, cost-efficient and low-risk solution using the most scalable, high-speed discrete memory available to the market. For more information, visit www.micron.com.

“With our GDDR6N for Networking announcement at the Linley Processor Conference last October and considerable interest from automotive customers, Micron continues to leverage our extensive experience and leadership in graphics memory,” said Tom Eby, senior vice president and general manager, Compute and Networking Business Unit at Micron. “This solution promises to unlock GDDR6 performance for a new wave of exciting and innovative products.”

“We are excited to work with our memory partners to deliver the best possible GDDR6 memory solution. Initially designed for high-performance graphics, the high bandwidth delivered by GDDR6 makes it ideal for other data-intensive applications like AI, ADAS (advanced driver assistance systems), and high-speed networking,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division.   “Leveraging nearly 30 years of experience in high-speed interface design, we are proud to be the first IP provider to offer a PHY solution for GDDR6 and continue our position on the leading edge of industry standards.”

“Northwest Logic’s is adapting its widely used, silicon-proven Memory Controller solution to support GDDR6 memory.  The fully configurable, high-performance GDDR6 Controller will be fully integrated, verified and delivered with the Rambus GDDR6 PHY enabling customer to quickly and reliably create GDDR6 designs,” said Brian Daellenbach, president of Northwest Logic.

“Avery is extending our proven line of memory models to support GDDR6.  These models provide significant performance monitoring and other useful features not found in the memory vendor models.   The Avery GDDR6 memory models will enable GDDR6-based SoC designs to be robustly verified and performance-optimized quickly and effectively,” said Chris Browy, vice president of sales and marketing for Avery Design.

About Micron
We are an industry leader in innovative memory and storage solutions. Through our global brands — Micron®, Crucial®, and Ballistix® — our broad portfolio of high-performance memory and storage technologies, including DRAM, NAND, NOR Flash, and 3D XPoint™ memory, is transforming how the world uses information to enrich life. Backed by nearly 40 years of technology leadership, our memory and storage solutions enable disruptive trends, including artificial intelligence, machine learning, and autonomous vehicles in key market segments like cloud, data center, networking, and mobile. Our common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology, Inc., visit micron.com.

About Rambus Inc.
Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products power and secure diverse applications, including Big Data, Internet of Things (IoT) security, mobile payments, and smart ticketing. For more information, visit rambus.com.

About Northwest Logic
Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance PCI Express Solution (PCI Express 4.0/3.0/2.1/1.1 cores, DMA cores and drivers), Memory Interface Solution (GDDR6, HBM2, DDR4/3, LPDDR4/3, MRAM), and MIPI Solution (CSI-2, DSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com.

About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

Rambus Announces GDDR6 Memory PHY for AI, Automotive and Networking Applications

High-performance GDDR6 PHY solution supports data rates up to 16Gbps

SUNNYVALE, Calif., Jan. 23, 2018 – Rambus Inc. (NASDAQ: RMBS) today announced the GDDR6 (Graphics Double Data Rate) Memory PHY IP Core targeted for high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking. Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the Rambus GDDR6 PHY architecture will provide the industry’s highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques.

“The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles, and high-speed networking,” said Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division. “We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications.”

Rambus GDDR6 Memory PHY Technical Highlights:

  • Standards compliant
  • Flexible delivery of IP core: works with ASIC/SoC layout requirements
  • Speed bins: 12 Gbps, 14 Gbps, 16 Gbps
  • 2 x 16 bit Channels, for a maximum bandwidth of 512 Gbps

Demonstration Details at DesignCon 2018
At DesignCon from Jan. 31 – Feb. 1, 2018 in Santa Clara, California, Rambus will demonstrate a memory channel signaling at GDDR6 speeds. Rambus will also present, “High-speed memory architectures for next-generation applications,” starting at 3:45pm PT on Jan. 31 in the room, “Great America 3,” that will discuss GDDR6 as well as other leading technologies. Visit Rambus at Booth 627 to learn more about GDDR6 applications.

For more information on Rambus GDDR6 technology, please visit https://www.rambus.com/gddr6.

Rambus Validates Interoperability of DDR4 High-performance Memory IP Solution for Arm-based Datacenter Systems

Rambus DDR4 3200 PHY, Arm CoreLink Dynamic Memory Controller provide comprehensive solution for datacenter and communications

SUNNYVALE, Calif. – Oct. 19, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced the validated interoperability of the Rambus DDR4 PHY and the Arm® CoreLink™ DMC-620 Dynamic Memory Controller. Together, these IP blocks offer speeds of up to 3200 Mbps, the highest performance memory speed available on the market. This partnership provides a verified solution to chip designers, reducing design time and improving time-to-market for demanding datacenter and communications applications.

“With rising chip design and IP integration costs, these pre-validated solutions from Rambus and Arm provide customers with an easy path to implementation and the peace of mind of a proven solution,” said Hemant Dhulla, vice president of product of Rambus Memory and Interfaces Division. “Rambus strives to work with companies like Arm that are leaders in the IP ecosystem to deliver high-quality, comprehensive solutions to the market.”

The CoreLink DMC-620 Dynamic Memory Controller is a fast, single-port Coherent Hub Interface (CHI) for transferring data from its CoreLink CMN-600 (Coherent Mesh Network) to the Rambus DDR4 memory PHY. CoreLink DMC-620 offers a combination of benefits to power, cost, and performance and guarantees interoperability with the Rambus DDR4 PHY, proven at speeds up to 3200 Mbps.

“Design teams face complex challenges in scaling the number of computing cores for advanced datacenter SoCs, while minimizing integration and testing time to ensure faster time-to-market,” said Jeff Defilippi, senior product manager, Infrastructure Business Unit, Arm. “Our collaboration with Rambus removes another degree of difficulty in designing purpose-built SoCs, resulting in higher-performing systems built for the most demanding cloud and enterprise workloads.”

The Rambus DDR4 memory PHY and CoreLink DMC-620 are both DFI 4.0 compliant, allowing the PHY and memory controller to interoperate. The Rambus memory PHY is fully JEDEC compliant to the DDR4 and DDR3/3L/3U standards. The Rambus silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution. For additional information on Rambus DDR4 PHY solutions, please visit rambus.com/ddrnphys.

Rambus and Northwest Logic Certify Interoperability of HBM2 Interface Solution for High-performance Networking and Data Center Applications

Integrated HBM2 PHY and Memory Controller provide validated, standards-compliant memory subsystem with superior signal integrity and reliability

SUNNYVALE, Calif. – Aug. 23, 2017 – Rambus Inc. (NASDAQ: RMBS), an innovator in semiconductor and IP products, today announced validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The solution builds on the growing ecosystem of Rambus partner products that interoperate with its latest HBM2 PHY IP core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets that require the maximum amount of bandwidth available through HBM2.

“Our work with Northwest Logic gives Rambus the functionality to provide a verified solution that reduces the engineering workload and time to market for chip designers” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “As Rambus extends its footprint in PHY support for leading-edge technologies, collaborative interoperability is essential for our end customers that demand early adoption. Memory interfaces are increasingly important in today’s new workloads, and the combination of Rambus HBM2 and Northwest Logic’ HBM2 Memory Controller core is a natural fit to support customer demands on both sides.”

The Northwest Logic HBM2 Memory Controller Cores are optimized for use in both ASICs and FPGAs, and support full-rate, half-rate and quarter-rate operations. The cores provide a solution that can be configured to exact customer requirements, are silicon-proven and are verified with the Rambus HBM2 PHY.

“Our HBM2 Memory Controller Core has been successfully deployed in a wide variety of customer systems demonstrating high reliability and performance,” said Brian Daellenbach, president of Northwest Logic. “We are excited to offer a complete HBM2 solution with Rambus ensuring our customers achieve the best possible combined memory solution for their high data demands.”

The Rambus HBM2 PHY and Northwest Logic HBM2 Memory Controller are each fully JEDEC compliant to the HBM2 standard, allowing the PHY and memory controller to interoperate. The Rambus HBM2 PHY is a high-performance memory IP core that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed, delivering higher efficiency and lower power consumption compared to other memory solutions on the market. For additional information on Rambus HBM2 PHY solutions, please visit https://www.rambus.com/memory-and-interfaces/ddrn-phys/hbm/

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Company website: rambus.com
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About Rambus Memory and Interfaces Division 
The Rambus Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus products deliver improved time-to-market and first-time-right quality.

About Rambus Inc.
Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile payments, and smart ticketing. At Rambus, we are makers of better. For more information, visit rambus.com.

Rambus Introduces High Bandwidth Memory PHY on GLOBALFOUNDRIES FX-14™ ASIC Platform using 14nm LPP Process Technology

High-performance, power-efficient memory solution designed for today’s data centers

SUNNYVALE, Calif. – February 7, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced the availability of its High Bandwidth Memory (HBM) Gen2 PHY developed for GLOBALFOUNDRIES high-performance FX-14TM ASIC Platform. Built on the GLOBALFOUNDRIES 14nm FinFET (14LPP) process technology, the Rambus HBM PHY is aimed at networking and data center applications and designed for systems that require low latency and high bandwidth memory. This PHY is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, enabling a total bandwidth of 256 GB/s to meet the needs of today’s most data-intensive tasks.

“Data center needs are continuously changing and we are at the forefront of delivering memory interface technology designed to meet today’s most demanding workloads,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces division. “Through our collaboration with GLOBALFOUNDRIES, we are delivering a comprehensive and robust solution for high-performance data center and networking applications. Our HBM offering will allow data center solution developers to bring high performance memory closer to the CPU, thus reducing latency and improving the system throughput.”

“With the rise of cloud computing and the growing needs of Big Data, the computing power of data centers is burdened more than ever and hardware manufacturers are being called upon to deliver new solutions that can meet these challenges,” said Kevin O’Buckley, vice president product development GLOBALFOUNDRIES. “Working together with Rambus enables us to provide ASIC solutions to our customers with increased memory capacity and bandwidth, with improved power efficiency. This HBM innovation complements other advanced chip to chip interfaces in our ASIC platform, including our industry leading 56G Long Reach SerDes technology.”

The Rambus HBM PHY delivers high performance with lower power consumption when compared to other memory solutions. It combines 2.5D packaging with a wider interface (1024 bits) at a lower clock speed, which results in a higher overall throughput while remaining energy efficient for even the most high-performance computing applications. Rambus experts perform complete signal and power integrity analysis on the entire 2.5D systems to ensure all signal and thermal requirements are met.

The HBM PHY is another key component in Rambus’ memory and SerDes high-speed interface IP portfolio for networking and data center applications. For additional information on Rambus Memory and Interfaces solutions, please visit rambus.com/memory-and-interfaces.

Follow Rambus:
Company website: rambus.com
Rambus blog: rambusblog.com
Twitter: @rambusinc
LinkedIn: www.linkedin.com/company/rambus
Facebook: www.facebook.com/RambusInc 

Press contact:

Agnes Toan
Corporate Communications
(408) 462-8905
atoan@rambus.com