Memory PHYs

Highlights:

• Complementary product portfolio of PHYs and controllers further accelerates Rambus growth
• Expands solutions for data center, artificial intelligence (AI), machine learning (ML), communications and automotive applications
• Combined offerings, including HBM2, GDDR6, DDR4 and PCI Express (PCIe), create one-stop-shop for SoC designers

SUNNYVALE, Calif. and HILLSBORO, Ore. – July 29, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has signed a definitive agreement to acquire Northwest Logic, a market leader in memory, PCIe and MIPI digital controllers. Northwest Logic’s high-performance, high-quality and silicon-proven digital IP controller cores are optimized for use in both ASICs and FPGAs. Interface IP solutions consisting of a physical interface (PHY) and companion digital controller make it possible to optimize the transfer of data between chips and electronic devices. Every SoC design that uses a Memory or a PCIe or a MIPI PHY also needs to use a controller associated with it. The combination of complementary digital and physical IP portfolios from Northwest Logic and Rambus will create a one-stop-shop for customers.

“With this acquisition, we expand our leading product portfolio for high-performance markets such as data center, networking, artificial intelligence, machine learning and automotive,” said Hemant Dhulla, vice president and general manager of IP Cores at Rambus. “Northwest Logic’s innovative, best-in-class digital controllers complement Rambus’ proven strength in high-speed physical IP cores. Together, we will offer one of the most comprehensive high-performance interface IP solutions in the industry, leveraging our core strength in semiconductors, strong go-to-market advantage and global reach.”

Brian Daellenbach, president and CEO, Northwest Logic said: “Northwest Logic’s category-leading digital controllers fit perfectly with Rambus’ leadership portfolio of high-speed PHY solutions. This deal creates a one-stop-shop for SoC designers working on state-of-the-art applications across a broad range of high-performance markets. We look forward to continue serving our existing customers and working with our PHY partners.”

Critical to enabling the high performance of data center, networking, AI, ML and automotive applications, this acquisition will bring together the physical and digital IP core families from renowned market leaders to offer comprehensive memory and SerDes IP solutions for chip designers.

The transaction is expected to close in the current calendar quarter of 2019. Although this transaction will not materially impact 2019 results due to the expected timing of close and acquisition accounting, Rambus expects this acquisition to be accretive in 2020.

Forward-looking statements
Information set forth in this press release, including statements as to Rambus’ outlook and financial estimates and statements as to the expected timing, completion and effects of the proposed acquisition of Northwest Logic, constitute forward-looking statements within the meaning of the safe harbor provisions of the Private Securities Litigation Reform Act of 1995.

These statements are based on various assumptions and the current expectations of the management of Rambus and may not be accurate because of risks and uncertainties surrounding these assumptions and expectations. Factors listed below, as well as other factors, may cause actual results to differ significantly from these forward-looking statements. There is no guarantee that any of the events anticipated by these forward-looking statements will occur, or what effect they will have on the operations or financial condition of Rambus or Northwest Logic. Forward-looking statements included herein are made as of the date hereof, and Rambus undertakes no obligation to publicly update or revise any forward-looking statement unless required to do so by federal securities laws.

Major risks, uncertainties and assumptions include, but are not limited to: the expected benefits and costs of the transaction; management plans relating to the transaction; the expected timing of the completion of the transaction; the satisfaction of all closing conditions to the transaction; statements of the plans, strategies and objectives of Rambus for future operations; any statements regarding anticipated operational and financial results; any statements of expectation or belief; the risk that disruptions from the transaction will harm Rambus’ business; other factors described under “Risk Factors” in Rambus’ Annual Report on Form 10-K and Quarterly Reports on Form 10-Q; and any statements of assumptions underlying any of the foregoing.  It is not possible to predict or identify all such factors. Consequently, while the list of factors presented here is considered representative, no such list should be considered to be a complete statement of all potential risks and uncertainties.

BOISE, Idaho, Jan. 23, 2018 (GLOBE NEWSWIRE) — Micron Technology, Inc. (NASDAQ:MU), a leading memory and storage provider, today announced with Rambus Inc., Northwest Logic and Avery Design, their efforts to deliver a comprehensive solution for GDDR6, the world’s fastest discrete memory. This first-of-its-kind solution would enable GDDR6 use in advanced applications such as high-performance networking, autonomous vehicles, artificial intelligence and 5G infrastructure.

Prior generations of GDDR memories, enabled by GPU vendors, were focused exclusively on the graphics market. While this allowed graphics and game console designs to take advantage of the significant performance advantage offered by GDDR, other applications could not because the necessary building blocks were not available.

This comprehensive solution brings together the unique contributions of each company to solve that problem, extending the reach and benefit of GDDR6 well beyond its traditional graphics market. The solution would include:

• GDDR6 Memory (Micron)
• GDDR6 PHY (Rambus)
• GDDR6 Controller (Northwest Logic)
• GDDR6 Verification IP (Avery Design)

Targeting up to 64GB/s, GDDR6 brings a significant improvement over the fastest available DDR4. This unprecedented level of single-chip performance, using proven, industry-standard BGA packaging provides designers a powerful, cost-efficient and low-risk solution using the most scalable, high-speed discrete memory available to the market. For more information, visit www.micron.com.

“With our GDDR6N for Networking announcement at the Linley Processor Conference last October and considerable interest from automotive customers, Micron continues to leverage our extensive experience and leadership in graphics memory,” said Tom Eby, senior vice president and general manager, Compute and Networking Business Unit at Micron. “This solution promises to unlock GDDR6 performance for a new wave of exciting and innovative products.”

“We are excited to work with our memory partners to deliver the best possible GDDR6 memory solution. Initially designed for high-performance graphics, the high bandwidth delivered by GDDR6 makes it ideal for other data-intensive applications like AI, ADAS (advanced driver assistance systems), and high-speed networking,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division.   “Leveraging nearly 30 years of experience in high-speed interface design, we are proud to be the first IP provider to offer a PHY solution for GDDR6 and continue our position on the leading edge of industry standards.”

“Northwest Logic’s is adapting its widely used, silicon-proven Memory Controller solution to support GDDR6 memory.  The fully configurable, high-performance GDDR6 Controller will be fully integrated, verified and delivered with the Rambus GDDR6 PHY enabling customer to quickly and reliably create GDDR6 designs,” said Brian Daellenbach, president of Northwest Logic.

“Avery is extending our proven line of memory models to support GDDR6.  These models provide significant performance monitoring and other useful features not found in the memory vendor models.   The Avery GDDR6 memory models will enable GDDR6-based SoC designs to be robustly verified and performance-optimized quickly and effectively,” said Chris Browy, vice president of sales and marketing for Avery Design.

About Micron
We are an industry leader in innovative memory and storage solutions. Through our global brands — Micron®, Crucial®, and Ballistix® — our broad portfolio of high-performance memory and storage technologies, including DRAM, NAND, NOR Flash, and 3D XPoint™ memory, is transforming how the world uses information to enrich life. Backed by nearly 40 years of technology leadership, our memory and storage solutions enable disruptive trends, including artificial intelligence, machine learning, and autonomous vehicles in key market segments like cloud, data center, networking, and mobile. Our common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology, Inc., visit micron.com.

About Rambus Inc.
Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products power and secure diverse applications, including Big Data, Internet of Things (IoT) security, mobile payments, and smart ticketing. For more information, visit rambus.com.

About Northwest Logic
Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance PCI Express Solution (PCI Express 4.0/3.0/2.1/1.1 cores, DMA cores and drivers), Memory Interface Solution (GDDR6, HBM2, DDR4/3, LPDDR4/3, MRAM), and MIPI Solution (CSI-2, DSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com.

About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

High-performance GDDR6 PHY solution supports data rates up to 16Gbps

SUNNYVALE, Calif., Jan. 23, 2018 – Rambus Inc. (NASDAQ: RMBS) today announced the GDDR6 (Graphics Double Data Rate) Memory PHY IP Core targeted for high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking. Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the Rambus GDDR6 PHY architecture will provide the industry’s highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques.

“The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles, and high-speed networking,” said Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division. “We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications.”

Rambus GDDR6 Memory PHY Technical Highlights:

• Standards compliant
• Flexible delivery of IP core: works with ASIC/SoC layout requirements
• Speed bins: 12 Gbps, 14 Gbps, 16 Gbps
• 2 x 16 bit Channels, for a maximum bandwidth of 512 Gbps

Demonstration Details at DesignCon 2018
At DesignCon from Jan. 31 – Feb. 1, 2018 in Santa Clara, California, Rambus will demonstrate a memory channel signaling at GDDR6 speeds. Rambus will also present, “High-speed memory architectures for next-generation applications,” starting at 3:45pm PT on Jan. 31 in the room, “Great America 3,” that will discuss GDDR6 as well as other leading technologies. Visit Rambus at Booth 627 to learn more about GDDR6 applications.

For more information on Rambus GDDR6 technology, please visit https://www.rambus.com/gddr6.

Rambus DDR4 3200 PHY, Arm CoreLink Dynamic Memory Controller provide comprehensive solution for datacenter and communications

SUNNYVALE, Calif. – Oct. 19, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced the validated interoperability of the Rambus DDR4 PHY and the Arm^® CoreLink^™ DMC-620 Dynamic Memory Controller. Together, these IP blocks offer speeds of up to 3200 Mbps, the highest performance memory speed available on the market. This partnership provides a verified solution to chip designers, reducing design time and improving time-to-market for demanding datacenter and communications applications.

“With rising chip design and IP integration costs, these pre-validated solutions from Rambus and Arm provide customers with an easy path to implementation and the peace of mind of a proven solution,” said Hemant Dhulla, vice president of product of Rambus Memory and Interfaces Division. “Rambus strives to work with companies like Arm that are leaders in the IP ecosystem to deliver high-quality, comprehensive solutions to the market.”

The CoreLink DMC-620 Dynamic Memory Controller is a fast, single-port Coherent Hub Interface (CHI) for transferring data from its CoreLink CMN-600 (Coherent Mesh Network) to the Rambus DDR4 memory PHY. CoreLink DMC-620 offers a combination of benefits to power, cost, and performance and guarantees interoperability with the Rambus DDR4 PHY, proven at speeds up to 3200 Mbps.

“Design teams face complex challenges in scaling the number of computing cores for advanced datacenter SoCs, while minimizing integration and testing time to ensure faster time-to-market,” said Jeff Defilippi, senior product manager, Infrastructure Business Unit, Arm. “Our collaboration with Rambus removes another degree of difficulty in designing purpose-built SoCs, resulting in higher-performing systems built for the most demanding cloud and enterprise workloads.”

The Rambus DDR4 memory PHY and CoreLink DMC-620 are both DFI 4.0 compliant, allowing the PHY and memory controller to interoperate. The Rambus memory PHY is fully JEDEC compliant to the DDR4 and DDR3/3L/3U standards. The Rambus silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution. For additional information on Rambus DDR4 PHY solutions, please visit rambus.com/ddrnphys.