Found 292 Results

Demonstration of a CXL Interconnect on a FPGA-based design

In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus’ CXL Controller and CXL.mem test design.

What is PCIe 4.0? PCI Express 4 explained

PCI Express® 4.0 also known as PCIe 4.0 or PCIe Gen 4 is the fourth generation of Peripheral Component Interconnect Express (PCI express) expansion bus specifications, which are developed, published, and maintained by the PCI Special Interest Group (PCI-SIG). It is an open standard. In this blog, you’ll learn all about PCI express 4 performance […]

Side-channel attacks explained: everything you need to know

In this blog post, we take an in-depth look at the world of side-channel attacks. We describe how side-channel attacks work and detail some of the most common attack methodologies. We also explore differential power analysis (DPA), an extremely powerful side-channel attack capable of obtaining and analyzing statistical measurements across multiple operations. In addition, we […]

PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases

Rambus announced this week that it demonstrated for the first time a PCI Express 5.0 Controller IP (PCIe 5 Controller) operating at 32 GT/s on a leading FPGA platform.  “We’ve achieved a new industry benchmark with the demonstration of our PCIe 5.0 Controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general […]

Rambus True Random Number Generator Certified to NIST SP 800-90B Standard

Cryptography depends on entropy. More specifically, every cryptographic protocol requires a source of non-deterministic (random) data to seed its security algorithms. While entropy is everywhere and, per the second law of thermodynamics, always increasing, it is exceedingly hard to create an unpredictable, statistically independent, uniformly distributed and protected source of data. In other words, creating a true random number generator is quite […]

Rambus Demonstrates Industry-first PCIe® 5.0 Digital Controller IP for FPGAs

Highlights:  Achieves industry-first demonstration of 32 GT/s PCIe 5.0 Digital Controller IP operation on leading FPGA platforms Expands use models for FPGAs by enabling multi-instance, PCIe 5.0 switching and bridging at 32 GT/s speeds Enhances performance and capabilities of FPGAs for use in emulation and prototyping, test and measurement, aerospace and defense, and storage and […]

PCIe 5.0 Multi-port Switch Product Brief

The Rambus PCIe 5.0 Multi-port Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports.

PCIe 2.1 Controller

PCIe 2.1 Controller Contact Us The PCIe 2.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 2.1 performance with great design flexibility and ease of integration. It is backward compatible with the PCIe 1.1 specification. A PCIe 2.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency […]

PCIe Controller for USB4

PCIe Controller for USB4 Contact Us The PCIe Controller for USB4 (formerly XpressRICH) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA implementations. There is also a PCIe Controller for USB4 with AXI version (formerly XpressRICH-AXI) with support for the AMBA AXI protocol specification. ContactProduct Briefs PCIe for USB4PCIe for USB4 […]

CCIX 1.1 Controller

CCIX 1.1 Controller Contact Us The CCIX 1.1 Controller (formerly XpressCCIX) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA implementations. There is also a CCIX 1.1 Controller with AXI version (formerly XpressCCIX-AXI) with support for the AMBA AXI protocol specification. ContactProduct Briefs CCIX 1.1 CCIX 1.1 with AXI How the […]

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