ZUC-IP-48 3GPP ZUC Accelerators
The ZUC-IP-48 (EIP-48) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as specified by 3GPP and ETSI. Designed for fast integration, low gate count and full transforms, the ZUC-IP-48 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed SoCs for base stations or other equipment requiring 3GPP support.
Contact3GPP ZUC-48 family of accelerators.
Available in 3 configurations / performance grades.
Targeting Base Station designs.
How the ZUC-IP-48 3GPP ZUC Accelerators work
The ZUC-IP-48 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the ZUC-IP-48 is the cipher core embedded in some PacketEngine-IP-97/196/197 protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges from 4 to 20 Gbps depending on the configuration, area and frequency. Gate count is 20K to 30K gates depending on the configuration. Supported modes: 128-EEA3 and 128-EIA3
Rambus also offers accelerators for the other 3GPP algorithms.
ZUC-IP-48 Information
Key benefits:
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations.
- World-class technical support
Features:
- Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface.
- Includes key scheduling hardware
- Supported modes: 128-EEA3 and 128-EIA3
- Fully synchronous design
- Low Speed, High Speed versions
