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DDR3 Controller

DDR3 Controller

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The Rambus DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications.

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DDR3 Controller Product BriefProduct Brief

How a DDR3 Interface Subsystem works

The Rambus DDR3 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic. The Rambus DDR3 controller can be paired with 3rd-party or customer PHY solutions.

DDR3 Memory Interface Subsystem
DDR3 Memory Interface Subsystem

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Mbps) Max. Application
DDR3800 to 2133IoT, Edge

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Inside Secure

Rambus Completes Acquisition of the Verimatrix Silicon IP, Secure Protocols and Provisioning Business

On December 8th, we announced the successful completion of our acquisition of the Verimatrix silicon IP, secure protocols and provisioning business, formerly Inside Secure.  This acquisition brings together a combined portfolio of products, including the secure silicon IP and provisioning solutions from both companies, creating the most comprehensive silicon-proven security IP portfolio in the industry. We welcome the Verimatrix silicon IP and secure protocols team to Rambus and are excited about the solutions we will create together for our customers.

This site provides additional information on the transaction and related documents.

Silicon IP

The Silicon IP products of the former Inside Secure can now be found under Root of Trust, Protocol Engines, Crypto Accelerator Cores, and Anti-Counterfeiting. Direct links to the Silicon IP products are found below:

Inside Secure Root of Trust
MACsec Engines
Multi-Protocol Engines for IPsec, TLS and SSL
High Speed Public Key Accelerator
Basic Crypto Blocks
Circuit Camouflage Technology

December 8, 2019
Rambus Completes Acquisition of the Verimatrix Silicon IP, Secure Protocols and Provisioning Business

September 11, 2019
Rambus Signs Agreement to Acquire Silicon IP and Secure Protocols Business from Verimatrix

September 3, 2019
Rambus to Acquire Silicon IP and Secure Protocols Business from Verimatrix, Creating Global Authority in Semiconductor Security IP

SEC Filings
Form 8-K

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Data and Communication

The Data and Communications products include software toolkits for MACsec, IPsec, TLS and more. These products can now be found at Software Protocols. Direct links to the software toolkit families are found below:

Secure Communication Toolkits (MACsec, TLS, IPsec)
IoT Security Framework (FIPS Security, Secure Boot)
Mobile Device Security (VPN Client, DAR)

Secure Provisioning

Now part of a portfolio of solutions that provision and secure billions of chips and devices annually, the provisioning offerings of the former Inside Secure can be found at Provisioning and Key Management. Direct links are found below:

Inside Secure Silicon Provisioning
Inside Secure Device Provisioning

For more information:

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PKA-IP-150

PKA-IP-150 RSA/ECC Public Key Accelerators

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The PKA-IP-150 is a family of Public Key Accelerators (PKA) IP cores designed for full scalability and an optimal “performance over gate count” deployment. Silicon-proven, the PKA-IP-150 address the unique high-speed, high-security requirements of semiconductor OEMs and provides a reliable and cost-effective IP solution that is easy to integrate into SoC designs. The PKA-IP-150 can be deployed in any semiconductor design that requires high performance key exchange or key generation with low power consumption, and can be provided with or without protection against side channel attacks.

The PKA-IP-150 public key accelerator combines the PKA-IP-28 and TRNG-IP-76 with an AMBA interface such as AXI or AHB.

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Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations

Public key signature generation, verification and key negotiation with little involvement of host

NIST CAVP compliant for FIPS 140-3

How the PKA-IP-150 works

The PKA-IP-150 accelerates the following basic operations in hardware:

  • Large vector addition, subtraction and combined addition/subtraction
  • Large vector bit shift right or left
  • Large vector multiplication, modulo and division (the 
latter generates both remainder and quotient)
  • Large vector compare and copy
PKA-IP-150 RSA/ECC Public Key Accelerators w w/o TRNG
PKA-IP-150 RSA/ECC Public Key Accelerators with TRNG

The included PKA-IP-28 core also accelerates the following complex operations, under control of an embedded sequencer microcontroller, using locally stored firmware:

  • Large vector unsigned value modular exponentiation
  • Large vector unsigned value modular exponentiation using the ‘Chinese Remainders Theorem’ (‘CRT’) method with pre-calculated Q inverse vector
  • Modular inversion: given A and M, calculate B such that ((AB) MOD M) = 1
  • Prime field ECC point addition/doubling on elliptic curve y2=x3+ax+b (mod p) with ‘p’ a prime number and ‘a’ and ‘b’ input values to the operation, adding identical points automatically performs point doubling – operation can be performed with affine and projective points
  • Prime field ECC point multiplication on elliptic curve y2=x3+ax+b (mod p) with ‘p’ a prime number and ‘a’ and ‘b’ input values to the operation – a version of the ‘Montgomery ladder’ algorithm, point randomization and point-on-curve checking are used to provide side channel attack protection 
The Sequencer firmware hides the fact that the modular exponentiations and ECC point multiplication are done using numbers in the Montgomery domain.
For improved performance of modular exponentiation operations, the Public Key Accelerator employs exponent recoding techniques that use a table with pre-calculated odd powers (filling this table is performed by the sequencer firmware). The smallest configurations can optionally use the ‘Montgomery Ladder’ algorithm for modular exponentiation (lower performance but fixed timing).
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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PKA-IP-150 Applications

PKA-IP-150 public key accelerators are suitable for a wide range of applications:

  • IoT, mobile, or other small gate count applications for secure boot, software public key signature checking and ‘occasional’ public key operations as used for IPsec and MACsec channel setup and firmware download signatures
  • Secure router boxes, secure network interfaces and SSL servers, where the PKA-IP-150 is used in medium to high performance (Elliptic Curve) Diffie-Hellman key negotiation engines
  • Hardware security modules, used in medium to high performance secure public key signature generator/checker engines 
 

The PKA-IP-150 is available in nine different performance configurations, ranging from 40K to 555K gates, each providing the full set of TRNG and PKA operations. The offer up to 4160-bit modulus size for modular exponentiations and 768-bit modulus for prime field ECC operations. The PKA-IP-150 is a security conscious design and can be provided with or without protection against side channel attacks.

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AES-IP-36

AES-IP-36 AES ECB/CBC/CTR accelerators

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The AES-IP-36 (EIP-36) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting ECB, CBC and CTR modes up to 12.8 Gbps @ 1GHz. Designed for fast integration, low gate count and full transforms, the AES-IP-36 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.

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AES family of accelerators.

Available in six configurations / performance grades.

Library element for security packet engines.

How the AES-IP-36 AES ECB/CBC/CTR Accelerators work

The AES-IP-36 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the AES-IP-36 is the cipher core embedded in all PacketEngine-IP-97/196/197 protocol-aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2.5 to 12.8 Gbps depending on the configuration and area. Gate count is between 23K and 52K gates depending on the configuration. Multiple AES-IP-36 cores can be cascaded.

Rambus also offers the AES-IP-39 that supports more AES modes and can be provided with counter measures including ones against side-channel attacks and fault injection attacks.

AES-IP-36 AES ECB/CBC/CTR Accelerators
AES-IP-36 AES ECB/CBC/CTR Accelerators

AES-IP-36 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

 Features:

  • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
  • Key sizes: 128, 192 and 256 bits
  • Includes key scheduling hardware
  • Feedback modes: ECB, CBC, CTR, OFB (128 bit), 
CFB (1, 8 and 128 bit)
  • Fully synchronous design
  • Low Speed, Medium Speed, High Speed versions
  • Encrypt-only versions (aimed at Counter Mode) for 
each speed version
 

Alternatives:

  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators

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AES-IP-37

AES-IP-37 AES Key Wrap Accelerators

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The AES-IP-37 (EIP-37) is IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394) up to 6 Gbps. Designed for fast integration, low gate count and full transforms, the AES-IP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems.

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AES key wrap family of accelerators.

Available in three configurations / performance grades.

Library element for storage solutions.

How the AES-IP-37 AES Key Wrap Accelerators work

The AES-IP-37 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance ranges from 1 to 6 Gbps depending on the configuration and area. Gate count is between 33K and 62K gates (excluding memory) depending on the configuration. Multiple AES-IP-37 cores can be cascaded.

Key wrap performance of the low gate count version is around 100K key wraps of unwraps (for 80-Byte key data), for the high end it is around 500K to 700K depending on frequency.

AES-IP-37 AES Key Wrap Accelerators
AES-IP-37 AES Key Wrap Accelerators
Watch Anti-Tampering Technologies Webinar

Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

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AES-IP-37 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
  • Key/KEK sizes: 128, 192 and 256 bits
  • Includes key scheduling hardware
  • Supported modes: NIST AES Key Wrap
  • Memory interface for key, intermediate and result data storage up to 4096 bits 
(Maximum supported input data block size is 512 bytes) 

  • Fully synchronous design
  • Low Speed, Medium Speed, High Speed versions
  • Support for two ECC (Error Correcting Code) bits from the external memory
  • Multiple IV loading options 

  • Unwrap result verification


 

Alternatives:

  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerators

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AES-IP-38

AES-IP-38 AES XTS/GCM Accelerators

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The AES-IP-38 (EIP-38) is IP for accelerating the AES symmetric cipher algorithm supporting GCM or XTS modes at extreme speeds up to 100 Gbps+ @ 850 MHz. Designed for fast integration, fast key switching and high performance, the AES-IP-38 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines. The IP supports Cipher Text Stealing (CTS) in combination with AES-XTS.

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AES XTS/GCM family of high speed accelerators.

Available in 12 configurations / performance grades.

Full key and data path integrity option.

How the AES-IP-38 AES XTS/GCM Accelerators work

The AES-IP-38 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the AES-IP-38 is the cipher core embedded in all MACSec protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Even though the Advanced Encryption Standard (AES) algorithm was designed to allow high-speed implementations, its regular feedback modes such as CBC, CFB, and OFB are not ideal for supporting very high-speed networking applications. The AES-GCM and AES-XTS algorithms do not use these regular AES feedback modes and allow very high-speed encryption and authentication by enabling an implementation to make use of parallelism. Typical uses cases for AES-GCM and AES-XTS are high-speed transmission (virtual private networking) and disk storage (protection of data at rest). For transmission protection, AES-GCM can for instance implement authenticated encryption at the network layer (IPsec) or at the data link layer (IEEE 802.1ae). The AES-GCM (Galois Counter Mode) has, since its publication in 2005, been used in many IPsec and MACsec applications. It is a very efficient algorithm, suitable to achieve very high performances. AES-XTS has been adopted by IEEE P1619 for protection of data at rest. The AES-IP-38 also supports the legacy AES-LRW algorithm. Within the AES-IP-38 product family a range of AES-XTS configurations is available that allows efficient key switching while maintaining throughputs for small sector sizes, ex- and including CTS.

Sustained performance for any object sizes ranges from 6 to 100 Gbps+ depending on the configuration and area. Gate count is between 90K and 650K gates depending on the configuration. Multiple AES-IP-38 cores can be cascaded. Tailored for storage solutions, a dedicated configuration offering full key and data path integrity is available.

AES-IP-38
AES-IP-38 AES XTS/GCM Accelerators

AES-IP-38 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Configuration Flexibility:

  • The AES-IP-38 accelerators are available in different configurations, suitable for different applications, and for meeting different gate count and throughput objectives. 

  • The AES-IP-38 is available in configurations supporting all modes, and dedicated XTS (and ECB) only configurations (EIP-38x-*), which are optimized for XTS operations having very limited overhead switching keys and direction.
 

Flexible, layered design:

  • In order to provide full flexibility and ease of use, the AES/GCM/XTS accelerators feature a layered design. The inner layer, the Engine, provides wide bus interfaces for Mode, Initialization Vector (IVs), Keys, and Data. These wide bus interfaces allow optimal data throughput and extremely fast context switching (that is, use of new Mode, IV, and Key values). Supports Cipher Text Stealing
  • For the non-high-speed cores (AES-IP-38b, AES-IP-38b-gcm, and AES-IP-38x-1) an outer layer is available. This outer layer has a 32- bit wide register interface. The input and output buffer registers inside the Shell allow for pipelining – input data and context information can be written and output data can be read while the Engine is performing an AES/GCM/XTS operation at the same time. This way, maximum through put is achieved using a 32-bit register interface.
  • The lower speed cores provide customers with the flexibility to be used with or without the Shell. The high-speed cores (AES-IP-38f, AES-IP-38o, AES-IP-38x-IP-5, AES-IP-38x-8, AES-IP-38x-10 and AES-IP-38x-14) must be integrated without the Shell to achieve the optimal performance.
  • Customers can also use the Shell logic as a basis for building a customized, width-constrained interface.
 

Data Integrity Protection:

  • On request, the AES-XTS only configurations are available with Data Integrity protection of the data path. All key and data inputs and outputs are extended with a parity bit per byte. The internal data path is extended to protect these vectors against single bit faults.
 

Features:

  • Wide bus interface
  • Basic AES encrypt and decrypt operations
  • Key sizes: 128, 192 and 256 bits
  • Key scheduling in hardware, allowing key, key size and 
direction changes every 13/15/17 clocks with zero impact 
on throughput
  • Hardware reverse (decrypt) key generation
  • Non-feedback modes: ECB and CTR
  • Feedback modes: CBC, OFB (128 bit), CFB (1-, 8- and 
128-bit)
  • AES-LRW with CTS1 (D5)
  • AES-XTS with CTS1 (D18)
  • AES-GCM (using AES-CTR mode and GHASH)
  • Basic GHASH operation (selecting no encryption)
  • Fully synchronous design
  • (Multiple) High-speed versions (encrypt only, en-/decrypt 
and XTS only)
  • XTS only configurations embed a dedicated CTS AES 
core allowing CTS to be applied every 10/12/14 clocks 
with zero impact on throughput
  • Optional data integrity protection
 

Alternatives:

  • AES-IP-32 AES ECB accelerators
  • AES-IP-36 AES ECB/CBC/CTR accelerators
  • AES-IP-37 AES Key Wrap accelerators
  • AES-IP-38 AES XTS/GCM accelerators
  • AES-IP-39 AES ECB/CBC/CTR/CCM/GCM accelerator

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