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HASH-IP-57

HASH-IP-57 hash accelerators, MD5, SHA-1, SHA-2, SHA-3 accelerators

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The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SHA-3 (FIPS-202), supporting the NIST MAC mode up to 6.4 Gbps @ 450MHz. Designed for fast integration, low gate count and full transforms, the HASH-IP-57 accelerators provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.

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Secure Hash family of accelerators.

Available in several configurations / performance grades.

Library element for platform security and packet engines

How the HASH-IP-57 works

The HASH-IP-57 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the HASH-IP-57 is the hash core embedded in the IPsec packet engines as well as VaultIP hardware root of trust cores providing support for MD5 and SHA Hash-based functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2 to 84 Gbps depending on the configuration and area. Gate counts ranges from 14K to 49K gates depending on the configuration.

HASH-IP-57 MD5, SHA-1, SHA-2, SHA-3 Accelerators
HASH-IP-57 MD5, SHA-1, SHA-2, SHA-3 Accelerators

HASH-IP-57 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface (1024-bit data, 512-bit digest) or 32 bit register interface
  • MD5, SHA-1, SHA-2, SHA-3
  • SHA-2/3 in 224/256/384/512 modes
  • Message puffing for all algorithms
  • Message data scheduling hardware
  • Hash context switching and state loading
  • Standard, high frequency and high performance versions available
  • Fully synchronous design
 

Alternative:

  • HMAC-IP-59 MD5, SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators

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HMAC-IP-59

HMAC-IP-59 MD5, SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators

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HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SHA-3 (FIPS-202), up to 8 Gbps. Designed for fast integration, low gate count and full transforms, the HMAC-IP-59 accelerators provide a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.

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Secure Hash-based HMAC family of accelerators

Available in several configurations / performance grades

Library element for platform security and packet engines

How the HMAC-IP-59 works

The HMAC-IP-59 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the HMAC-IP-59 is the hash core embedded in the IPsec packet engines as well as the VaultIP root of trust cores providing support for MD5 and SHA based Hash and HMAC functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2 to 8 Gbps, depending on the configuration and area. Gate counts ranges from 23K to 95K gates depending on the configuration.

HMAC-IP-59 MD5, SHA-1, SHA-2, SHA-3 based HMAC Accelerators
HMAC-IP-59 MD5, SHA-1, SHA-2, SHA-3 based HMAC Accelerators

HMAC-IP-59 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface
  • Supporting HMAC and Basic Hash operations for all algorithms: MD5, SHA-1, SHA-2 (224, 256, 384, 512), SHA-3 (224, 256, 384, 512)
  • MAC Key XOR and Message padding
  • Message data scheduling hardware
  • Calculation of “inner digest” and “outer digest” from a MAC Key input
  • Calculation of “inner hash” and “outer hash” from a MAC Key input or “inner digest” and “outer digest” input
  • MAC Key sizes shorter, equal and longer than algorithm block size
  • Hash and HMAC context switching
  • Continued hash / HMAC support
  • Standard, high frequency and high performance versions available
  • Secure hash standard-compliant FIPS-180-2, FIPS-180-3, FIPS-180-4
  • HMAC support for all algorithms, compliant with FIPS-198-1, FIPS-198
  • Fully synchronous design
 

Alternative:

  • HASH-IP-57 / EIP-57 Hash MD5, SHA-1, SHA-2, SHA-3

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POLY-IP-53

POLY-IP-53 Poly1305-based MAC Accelerators

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Poly-IP-53 (EIP-53) is IP for accelerating the Poly1305 hash-based message authentication algorithm (RFC7539), supporting the NIST MAC mode up to 6.4 Gbps @ 450MHz. Designed for fast integration, low gate count and full transforms, the Poly-IP-53 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.

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Poly1305 family of accelerators

Available in several configurations / performance grades

Supporting TLS1.3 IoT HomeKit

How the POLY-IP-53 works

The Poly-IP-53 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the Poly-IP-53 is the cipher core embedded in the Vault-IP-140 platform security engines providing support for TLS1.3 and HomeKit IoT applications (Poly1305 is also available as software implementation in the VaultIP core). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 1 to 6.4 Gbps depending on the configuration and area. Gate count is around 50K gates depending on the configuration.

Rambus also offers the required ChaCha20 cipher to match the Poly1305 algorithm to match the HomeKit.

POLY-IP-53 Poly1305 based MAC Accelerators
POLY-IP-53 Poly1305 based MAC Accelerators

POLY-IP-53 Information

Key benefits:

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support
 

Features:

  • Wide bus interface (128-bit data, 128-bit keys, 135-bit digest) or 32-bit register interface
  • Key size: 128 bits
  • Includes initialization stage
  • Supports continuation mode
  • Fully synchronous design

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PKA-IP-28

PKA-IP-28 RSA/ECC Public Key Accelerators

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The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate count” deployment. Proven in silicon, the PKA-IP-28 public key accelerator addresses the unique needs of semiconductor OEMs and provides a reliable and cost-effective solution that is easy to integrate into SoC designs. The PKA-IP-28 can be deployed in any semiconductor design that requires high performance/low power consumption key exchange or key generation.

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Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
Public key signature generation, verification and key negotiation with little involvement of host

NIST CAVP compliant for FIPS 140-3

How the PKA-IP-28 works

The PKA-IP-28 accelerates the following basic operations in hardware:

  • Large vector addition, subtraction and combined addition/subtraction
  • Large vector bit shift right or left
  • Large vector multiplication, modulo and division (the 
latter generates both remainder and quotient)
  • Large vector compare and copy
PKA-IP-28 RSA/ECC Public Key Accelerators
PKA-IP-28 RSA/ECC Public Key Accelerators

The PKA-IP-28 also accelerates the following complex operations, under control of an embedded sequencer microcontroller, using locally stored firmware:

  • Large vector unsigned value modular exponentiation
  • Large vector unsigned value modular exponentiation using the ‘Chinese Remainders Theorem’ (‘CRT’) method with pre-calculated Q inverse vector
  • Modular inversion: given A and M, calculate B such that ((AB) MOD M) = 1
  • Prime field ECC point addition/doubling on elliptic curve y2=x3+ax+b (mod p) with ‘p’ a prime number and ‘a’ and ‘b’ input values to the operation, adding identical points automatically performs point doubling – operation can be performed with affine and projective points
  • Prime field ECC point multiplication on elliptic curve y2=x3+ax+b (mod p) with ‘p’ a prime number and ‘a’ and ‘b’ input values to the operation – a version of the ‘Montgomery ladder’ algorithm, point randomization and point-on-curve checking are used to provide side channel attack protection 
The Sequencer firmware hides the fact that the modular exponentiations and ECC point multiplication are done using numbers in the Montgomery domain.
For improved performance of modular exponentiation operations, the Public Key Accelerator employs exponent recoding techniques that use a table with pre-calculated odd powers (filling this table is performed by the sequencer firmware). The smallest configurations can optionally use the ‘Montgomery Ladder’ algorithm for modular exponentiation (lower performance but fixed timing).

PKA-IP-28 Applications

PKA-IP-28 public key accelerators are suitable for a wide range of applications:

  • IoT, mobile, or other small gate count applications for secure boot, software public key signature checking and ‘occasional’ public key operations as used for IPsec and MACsec channel setup and firmware download signatures
  • Secure router boxes, secure network interfaces and SSL servers, where the PKA-IP-28 is used in medium to high performance (Elliptic Curve) Diffie-Hellman key negotiation engines
  • Hardware security modules, used in medium to high performance secure public key signature generator/checker engines

The PKA-IP-28 is available in nine different performance configurations ranging from 19K to 515K gates, each providing the full set of PKA operations with up to 4160-bit modulus size for modular exponentiations and 768-bit modulus for prime field ECC operations. The PKA-IP-28 is a security conscious design and can be provided with or without protection against side channel attacks. The PKA-IP-28 is also available as embedded PKA in our VaultIP and PKA-IP-154 product lines.

PKA-IP-28 Performance and Interfaces

Frequency

  • 45nm: 400MHz
  • 28nm: 700Mhz
  • 16nm: 800MHz
 

In 28nm, performance of 700MHz is possible. In 16nm, 800MHz is possible. Performance scales with smaller process nodes.

Host Interfaces:

  • TCM target interface for configuration and control
  • Also available as PKA-IP-150 with AMBA slave (AXI or AHB).
  • Local memories:
    • 2K or 4K Byte data RAM (1K and 8K Byte possible)
    • 2K … 4K words of 32-bits program RAM (ROM optional)
    • 47 … 132 words of 32-bits FIFO RAM for faster configurations
    • Interrupt outputs (functional and alarm)

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TRNG-IP-76 (True Random Number Generator)

TRNG-IP-76 FIPS-Certified True Random Number Generators

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The TRNG-IP-76 is a NIST ESV certified, FIPS (SP800-90A/B/C) Ring Oscillator-based True Random Number Generator IP core for True Random Number Generation (TRNG) with an optional post-processor and several internal self-tests. Designed for easy integration into ASICs and SOCs, the 100% digital standard cell based TRNG-IP-76 provides a reliable and cost-effective embedded IP solution for our customer’s SoCs.

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Non-deterministic Random Number Generator, FIPS-140 SP800-90A/B compliant, ESV certified for NRBGs and DRBGs (#E167).

High performance, low power, fully digital, standard cell only, supports all CMOS nodes.

Available as standalone RBG or embedded in the Rambus RT-130, RT-630, RT-660 Root of Trusts

How the TRNG-IP-76 works

TRNGs are typically deployed in semiconductors for securing data communications, electronic transactions, and data storage. They are used for generation of keys, initialization vectors, cookies, and nonces. Additionally, TRNGs can also be used for statistical sampling, communications protocol timers, as well as noise generation.

To provide a hardware-based, nondeterministic noise source the TRNG-IP-76 uses a state-of-the-art reliable free running oscillator (FRO) implementation. This allows stable operation across very wide process, voltage, and temperature (PVT) ranges, as required for modern process node (45nm and below) semiconductors.

When running asynchronously, the FROs accumulate a timing jitter largely due to shot noise effects. When the signal is sampled, this jitter causes unpredictability of the outcome, thereby providing some entropy. These samples feed a complex, non-linear combinatorial circuit that produces the final TRNG output. This function is referred to as a hardware-implemented Non-deterministic Random Bit Generator (NRBG).

TRNG-IP-76 (EIP-76) family of FIPS approved True Random Generators
TRNG-IP-76 (EIP-76) family of FIPS approved True Random Generators

The TRNG-IP-76 is a security aware design:

  • Patented test circuits on the oscillators that detect locking to periodic signals.
  • Repeating output data detection on NRBG and DRBG (compliant with FIPS-140).
  • Hardware-implemented health-tests, including ‘Repetition Count Test’ and ‘Adaptive Proportion Test’ (compliant with SP800-90B).
  • Secure random data buffer wipe-after-read and zeroize functions (compliant with FIPS-140).
  • Secure reading mode where data is only available on request, for a (configurable) limited time.
  • Automatic shutdown on fatal errors.
  • Various on-line and off-line integrity and known-answer tests on the Conditioning Function, DRBG and self-test circuits.
 

The TRNG-IP-76 is compliant with Federal Information Processing Standards (FIPS) Publication 140-3, facilitating system certification. The design is compliant with the latest versions for NIST SP800-90A/B/C. A NIST SP800-90 Deterministic Random Bit Generator (DRBG) is available for the required post processing. The TRNG-IP-76 is ESV certified and is FIPS-approved when integrated into Rambus Root of Trust solutions.

The TRNG-IP-76 is silicon proven, and its flexible, layered design makes it easy to integrate into SoCs. A driver development kit is included.

Features of the TRNG-IP-76

Standard configurations of the TRNG-IP-76 include:

  • TRNG-IP-76a-8: base configuration with 8 FROs
  • TRNG-IP-76d-8-SHA2: 8 FROs and DRBG
  • TRNG-IP-76d-8-BC_DF: 8 FROs, DRBG with BC_DF

All configurations operate with eight Free Running Oscillators (FROs).

In addition to the base configuration, the TRNG-IP-76 offers several configurable options that are described in the NIST specification SP800-90c draft:

  • A vetted SHA-2 based conditioning component (SP800-90B), can be embedded in the NRBG. This conditioning component is responsible for increasing the entropy rate to produce full-entropy bit strings used to seed a DRBG.
  • A Deterministic Random Bit Generator, based on AES in counter mode, can be added. It can be coupled with a block cipher derivation function in case no conditioning component is present (compliant with SP800-90A).
Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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Circuit Camouflage Technology

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Circuit Camouflage Technology

Rambus Circuit Camouflage Technology protects semiconductors against reverse engineering and cloning by competitors, state actors, and nefarious parties. Circuit Camouflage is an anti-reverse engineering and anti-cloning technology designed for commercial and government applications. It provides protection at the standard-cell level, using proprietary techniques that significantly decrease the accuracy of automated tools used in the reverse engineering process.

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How Circuit Camouflage Works

Reverse engineering a circuit is done via the use of destructive ‘de-layering’ techniques. The reverse engineering party first de-lids the chip’s package and takes an image of the silicon chip. Then, specialty equipment carefully removes a very thin layer of the silicon. At this point, an image of the now exposed layer is taken. This process is repeated until the entire silicon chip has been de-layered and photographed. The resulting images are then digitized, aligned and combined. Automated tools then analyze the visual model to build a functional model of the chip, resulting in a full netlist and a hierarchical RTL of the design.

Rambus Circuit Camouflage Technology is designed to complicate this process through the integration of multiple “lookalike cells” into a chip’s design. These cells are either optically indistinguishable from the standard cells used throughout the design, or they may appear like nothing the reverse engineer has ever seen. Camouflaged cells can also be enabled to perform logic functions that are different than what would be expected by visual analysis. Together, these approaches introduce errors into the reverse-engineering process, resulting in an incorrect netlist recovered from the silicon.

Normal AND2 gate
Normal AND2 gate
Camouflage AND2 gate

The camouflage AND2 gate appears identical to the normal AND2 gate, but performs a different logic function.

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Anti-Tampering Technologies

The design of chip anti-tamper protection needs to adapt and scale with rising threats. Adversaries range from high school hackers to well-funded state actors. Given the threats, it’s useful to think about anti-tamper countermeasures as a hierarchy of safeguards that parallel the type, effort and expense of attacks. Watch this webinar to learn the eleven kinds of tampering attacks and their required skills and resources, and countermeasures for each of these attacks.

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Camouflage cells are typically custom-created for individual chip OEMs or specific chip designs, ensuring that an adversary’s knowledge gained from a prior design doesn’t inform reverse engineering of a new design. Circuit Camouflage uses foundry standard processes, standard tools and design methodologies, and doesn’t rely on coatings or shields. It provides a high return on investment for silicon manufacturers and chip makers desiring intellectual property protection while having products in environments with a high risk of attack.

SmartFill: Protecting Critical IP

Rambus SmartFill technology provides high tamper-resistance from unauthorized modifications to the design by eliminating the whitespace in the post place-and-route circuitry. This both complicates reverse-engineering, as well as denies attackers any space in which to insert a trojan circuit without destroying the underlying function of the chip.

Implementation in Devices

Protected by more than 50 US and international patents, Rambus has developed the know-how and proprietary trade secret techniques that uniquely position us to implement these designs. We offer training and licensing options, enabling your design team to implement Circuit Camouflage Technology in your devices. We also offer a range of courses in hardening silicon IP to reverse engineering, cloning, and tamper attacks.

Rambus Circuit Camouflage and SmartFill technologies protect design secrets from competitors and counterfeiters through combating state-of-the-art circuit extraction attack vectors. They significantly extend the security life of your product, and are applicable to any CMOS process and digital design (analog camouflage IP also available). In practice for over 20 years, our techniques easily apply to standard cell design flow with minimal impacts to area, performance, and power consumption.

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The CryptoManager Root of Trust

Built around a custom RISC-V CPU, the Rambus CryptoManager Root of Trust (CMRT) is at the forefront of a new category of programmable hardware-based security cores. Siloed from the primary processor, it is designed to securely run sensitive code, processes and algorithms. More specifically, the CMRT provides the primary processor with a full suite of security services, such as secure boot and runtime integrity, remote attestation and broad crypto acceleration for symmetric and asymmetric algorithms.
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