As chip designers face greater requirements for security, they also have a growing number of options for secure silicon IP. They can build it themselves, use “free” IP that comes along with other components, use something open source, or obtain it from an IP vendor that specializes in security. There are pros and cons to each approach, but one consideration that is often overlooked is the need for certification for security and functional safety. This webinar will examine some of the common certification regimes, their costs and benefits, and how this impacts the selection of security IP.
HBM2E Controller Product Brief
HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
The Northwest Logic HBM2 Controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. With the Rambus HBM2 PHY it comprises a complete HBM2 memory interface subsystem.
GDDR6 Controller Product Brief
Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of compute-intensive applications including artificial intelligence (AI), data center and advanced driver assistance systems (ADAS).
The Northwest Logic GDDR6 Controller supports data rates of up to 20 Gbps per data pin. With the Rambus GDDR6 PHY, it comprises a complete GDDR6 memory interface subsystem.
DDR4 Controller Product Brief
The Northwest Logic DDR4 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. With the Rambus DDR4 PHY it comprises a complete DDR4 memory interface subsystem.
DDR3 Controller Product Brief
The Northwest Logic DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. With the Rambus DDR3 PHY it comprises a complete DDR3 memory interface subsystem.
Read-Modify-Write Core Product Brief
Part of a full suite of memory controller add-on cores, the Read-Modify-Write Core handles misaligned bursts when an Error Correction Code (ECC) is being used. Read-Modify-Write write operations are by their very nature inefficient. The Read-Modify-Write core implements a prefetch architecture that maximizes the memory bus utilization as efficiently as possible.
