Remember the Spectre and Meltdown security exploits from last year? Intel and AMD really hopes you don’t. Despite what they want you to believe, these speculative execution exploits aren’t going away, at least not with the solutions proposed so far. Instead of trying to fix each variant that comes along, a permanent fix will require a fundamental change to how CPUs are designed. The proposition? A “secure core” that make ensure your data stays safe from attackers, no matter what bugs they might try to exploit.
Interview with Russell McCullagh at Transport Ticketing Global
Rambus and GLOBALFOUNDRIES to Deliver High-Speed SerDes on 22FDX® for Communications and 5G Applications
32G PHY will deliver power efficiency and performance for next-generation wireline and wireless infrastructure
SUNNYVALE, Calif. – February 20, 2019 – Rambus Inc. (NASDAQ: RMBS), a leading provider of semiconductor and IP products, today announced the availability of 32G Multi-protocol SerDes PHY on GLOBALFOUNDRIES 22nm FD-SOI (22FDX®) platform for high-volume, high-performance applications. Designed to meet the performance requirements of high-speed wireline, wireless 5G infrastructure and data center applications, the SerDes PHY delivers data rates up to 32 Gbps and supports multiple standards including PCIe 4.0, JESD204B/C, CPRI, and Ethernet.
“Boasting increasingly high performance and network density, Rambus 28G and 32G SerDes will be critical to 5G infrastructure, wireless base stations and remote radio heads, autonomous vehicles, data center optical switches and highly anticipated technologies like artificial intelligence and machine learning inferencing, smart cities, and more,” said Hemant Dhulla, vice president and general manager of IP Cores at Rambus. “By developing our high-speed interfaces on GF’s leading 22FDX process, we are able to deliver the high performance alongside reduced power and area required for these applications.”
“Rambus and GF have a long history of delivering leading-edge solutions on our processes,” said John Kent, vice president of IP at GLOBALFOUNDRIES. “Working together with Rambus enables us to provide our clients with power and area optimized high-speed SerDes interfaces to deliver leadership system solutions, while maintaining compatibility with industry standards.”
The 28G and 32G Multi-protocol SerDes (MPS) PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. These comprehensive high-speed SerDes IP solutions are optimized for power and area in long-reach channels typical of communications, networking and data center applications — making this PHY ideal for challenging high-performance wireline and wireless infrastructure environments.
Learn More about SerDes PHY Solutions
The Rambus industry-standard interface offerings are high-quality, complete PHY solutions designed with a system-oriented approach to maximize flexibility in today’s most challenging system environments. For more information on Rambus SerDes PHYs, visit: rambus.com/serdes
Availability
Early access design customers for this PHY can engage with Rambus today. Licensing is also currently available.
Visit Rambus at Mobile World Congress 2019 in Barcelona, Spain
Please visit Rambus at Mobile World Congress in Booth #6H21 (Hall 6) at the Fira Gran Via.
Controllers Newsletter – Q1 2019
Northwest Logic’s PCI Express™ 5.0 Solution Available Now
Northwest Logic’s PCI Express 5.0 solution is available now including PCI Express 5.0 Core that is:
- PCI Express™ 5.0 specification compliant (32 Gbit/s lane rate support)
- x16, x8, x4, x2, x1 lane with bifurcation support
- Endpoint, Root Port, Switch support
- more
This solution also includes Northwest Logic’s family of Expresso DMA Cores and DMA Drivers which provide the maximum system throughput on a PCI Express link.
This PCI Express 5.0 solution provides a robust, high-performance platform for developing PCI Express™ 5.0 based products. It is currently available for use in ASIC platforms. Contact Northwest Logic for more information on how to start your PCIe™ 5.0 design now!
Northwest Logic’s GDDR6 Controller Core Available Now
Northwest Logic has delivered production versions of its GDDR6 Controller Core. The GDDR6 Controller Core supports single x32 or dual x16 controller configurations as well as GDDR6 clamshell mode. It includes queue-based look-ahead command processing and an optional command reordering function for maximum bus utilization. It also includes support for automatic retry when interface data errors are detected, and can be configured with in-band ECC checking as an add-on option. The GDDR6 controller solution can be delivered fully integrated and verified with the Rambus GDDR6 PHY. GDDR6 supports 60 GB/s transfer rates with a single device while utilizing proven BGA packaging and provides a significant performance advantage over DDR4. This enables highly differentiated solutions for high-performance networking, autonomous vehicles, artificial intelligence, and 5G infrastructure applications. Click here for Northwest Logic’s Memory Interface Solution information. Click here to review the Micron GDDR6 Technical Note.
Northwest Logic Delivering HBM2 Controller Core With HBM2E Support
Northwest Logic is delivering its HBM2 Controller solution with full support of the latest JEDEC standard (JESD235B). This standard, informally referred to as HBM2E, extends the supported HBM2 stack heights up to 12 high and channel densities up to 24 Gbit. At the same time, the HBM2 device providers are extending the supported data rates up to 3.2 Gb/s/pin for a total bandwidth of 400 Gbytes/s. “We are very pleased to provide comprehensive HBM2E support. This support further fortifies our industry leading HBM2 Controller solution” said Brian Daellenbach, President of Northwest Logic. Please contact Northwest Logic for more information.
Northwest Logic’s Low Latency HBM Support Released
Northwest Logic has collaborated with Renesas and eSilicon to deliver a comprehensive Low Latency HBM solution. Renesas’ Low Latency HBM devices support random memory accesses with high throughput and small data granularity making them attractive for a wide range of next generation applications. “We are excited to offer Low Latency HBM device support as part of our overall HBM2 solution,” said Brian Daellenbach, President at Northwest Logic. Northwest Logic and eSilicon provide a complete HBM2 controller and PHY solution with Low Latency HBM support. “eSilicon has verified our Low Latency HBM PHY and Northwest Logic’s controller in a 7nm process,” said Hugh Durdan, vice president, strategy and products at eSilicon. For more information please click on: Renesas Low Latency HBM, eSilicon PHY, or Northwest Logic Memory Controller.
Northwest Logic Includes Avery Memory Models In Its Deliveries
Northwest Logic’s memory controller deliveries now include an evaluation version of Avery Design Systems memory models. Avery’s full featured memory models include HBM2E, HBM2, GDDR6, DDR4 and LPDDR4 support; configurable device speeds and density, built-in protocol analyzer for debugging and performance analysis; and broad memory vendor device support. Avery’s memory models also support advanced device speeds much earlier than the memory device vendors, enabling designs to be future proofed. Please contact Northwest Logic or Avery Design Systems for more information.
Northwest Logic’s DSI Controller IP Used in Inova Semiconductors Multichannel Automotive SerDes Devices
Inova Semiconductors GmbH has just announced its latest Multichannel Automotive SerDes devices, the INAP565TAQ and INAP562RAQ. These new APIX3 devices utilize Northwest Logic’s MIPI® DSISM Host, DSISM Peripheral Controller cores to provide high speed video, data, audio and Ethernet connections over a 12 Gbps link up to 10m distance. The devices are being used by several well-known car brands and can connect Navigation displays, Cluster displays, Head up displays or Rear Seat entertainment. “We are very pleased with the quality, ease of integration and support provided by Northwest Logic. The DSI Peripheral is seamlessly integrated into the INAP565TAQ and the DSI Host is integrated in the INAP562R”, said Roland Neumann, Executive VP Engineering at Inova Semiconductor. Click here for more information.
Northwest Logic MIPI DSI-2 Host Controller and Mixel C-PHY/D-PHY Combo IP Integrated into Synaptics VXR7200 IC Enabling Next Generation VR Headsets
Synaptics achieved first-time silicon success supporting full-production-readiness with the NWL DSI-2 Host Controller and the Mixel Combo PHY. This IP is delivered fully integrated and validated. With D-PHY @2.5Gbs/lane for Legacy infrastructure and C-PHY support at 2.5Gsym/sec the, fully integrated IP provide the bandwidth and scan timing and interoperability required to eliminate screen door effects and enables the ability to read text. The VXR7200 is optimized for VR, AR, and MR dual displays headsets. Click here for the full press release.
Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance
Rapidly evolving workloads and exploding data volumes place great pressure on data-center compute, IO, and memory performance, and especially on memory capacity. Increasing memory capacity requires a commensurate reduction in memory cost per bit. DRAM technology scaling has been steadily delivering affordable capacity increases, but DRAM scaling is rapidly reaching physical limits. Other technologies such as Flash, enhanced Flash, Phase Change Memory, and Spin Torque Transfer Magnetic RAM hold promise for creating high capacity memories at lower cost per bit. However, these technologies have attributes that require careful management.

