Gary Hilson of the EE Times has covered Rambus’ recent announcement about the development of its R+ DDR4 PHY on GLOBALFOUNDRIES 14nm LPP process. As the journalist notes, the silicon is the first production-ready 3200 Mbps DDR4 PHY available on GLOBALFOUNDRIES Inc.’s FX-14 ASIC platform using its power-performance optimized 14nm LPP process.
“The Rambus R+ DDR4 PHY intellectual property uses Rambus’ proprietary R+ architecture, based on the DDR industry standard,” Hilson explained. “The PHY is part of the Rambus’ suite of memory and SerDes interface offerings for networking and data center applications. Meeting the performance and capacity demands of those segments [is] a heavy focus for the company.”
Frank Ferro, a senior director of product marketing at Rambus, told the publication that the DFI 4.0-compatible R+ DDR4 PHY will enable customers to differentiate their offerings with improved performance while still maintaining full compatibility with industry standard DDR4 and DDR3/3L/3U interfaces.
“This gets them ahead of the curve in terms of memory performance,” Ferro said.
Indeed, the R+ DDR4 PHY delivers data rates from 800 to 3200 Mbps in multiple memory sub-system options, including die down, DIMM and 3DS. It also supports 16 to 72-bit interfaces, along with single and multi-rank configurations. The overall goal, says Ferro, is to provide system designers with flexibility for both high performance and low power, which is where the GLOBALFOUNDRIES 14nm process comes in. Nevertheless, as Ferro emphasizes, while DDR4 provides a significant performance boost over DDR3, engineers are still finding it challenging to improve the interface between memory and the CPU.
“The CPUs can run faster, and they [have] multiple channels of local DRAM they are accessing, but the CPUs are only as good as the access to the memory,” he explained. “The interface is the key bottleneck in the system.”
Ferro told the EE Times that Rambus is using internal tools to analyze the physical connections between the CPU and the DIMMs. “That’s where the limits come in. I think there’s still a ways to go,” he added.
Another challenge, he notes, is balancing the trade-offs between density and bandwidth by looking at the physical loading onto the bus. Rambus, Ferro confirmed, is currently exploring technology to minimize the loading effect of DIMMs.
From a broader perspective, says Ferro, while the high performance computing (HPC) segment might be what comes to mind first, Rambus is looking to meet the needs of the Facebooks and Instagrams of the world as their data center requirements trickle down to the chip companies. To be sure, Rambus recently announced its intention to acquire Inphi’s memory interconnect business as well as Semtech’s Snowbush serial interface IP.