Frank Ferro, a Senior Director of Product Marketing at Rambus, recently participated in a Semiconductor Engineering roundtable discussion about 2.5D and advanced packaging.
According to Ferro, 2.5D can succeed if customer demand overcomes the additional engineering costs associated with the packaging process.
“Back in the mobile days when we started seeing 3D packaging, it was because we needed space. We needed to get more memory into a smaller footprint,” he explained. “Today we’re seeing bandwidth as a driver in the case of high bandwidth memory (HBM). There’s a need to create another tier in the hierarchy, so customers are interested in looking at the cost tradeoffs of 2.5D using silicon interposer, and HBM versus traditional DRAM. Are the economics there? Yes, for the people who really want it and need it. For the masses, we still have a way to go.”
Ferro also commented on the power aspect of 2.5D packaging.
“Power is important. If you look at HMC (Hybrid Memory Cube), it was really hot two years ago, but has fizzled since then. By serializing all those signals you need high-speed SerDes,” he continued. “And then you have to look at the power of high-speed SerDes, versus HBM, which is wide and relatively slow. Power in HMC might have been less complex when seen from a 2D to 3D evolution standpoint because it was similar, but HBM won out because of lower power and lower complexity.”
Perhaps most importantly, says Ferro, it is essential for the industry to fully understand the 2.5D supply chain.
“If you’re just delivering a chip, then you can ship that chip to the customer. But now you’ve got a memory vendor, an SoC vendor, and an interposer vendor,” Ferro explained. ”How do you test that memory? If something breaks, who’s responsible for it? Now there are pins you can’t physically get to anymore. Three companies have to work together, so you have to get all these companies talking together.”
Simply put, there is a real problem if something goes wrong.
“You’re responsible to the end customer, but in your supply chain, you are still subject to those effects. You make it easier for your end customer, but you still have to deal with it,” he added.
As we’ve previously discussed on Rambus Press, HBM design and implementation can be challenging, as 2.5D-packaging technology inevitably adds various manufacturing complexities, along with silicon interposer costs. To be sure, there are numerous expensive components mounted to the interposer, such as the SoC and multiple HBM devices. Another significant challenge involves routing thousands of signals (data + control + power/ground) via the interposer to the SOC for each HBM memory used.
Despite the above-mentioned challenges, HBM offers a number of distinct capabilities for a new digital age dominated by the IoT. These include moving memory closer to the CPU, while increasing both density and bandwidth. Indeed, HBM takes advantage of existing technologies to create another tier of memory, thus bolstering server memory architecture.