Rambus engineers Niall Sorensen and Malini Narayana Moorthi recently wrote an article for Semiconductor Engineering that takes an in-depth look at how to overcome high-speed SerDes IP integration challenges. As Sorensen and Moorthi note, internet traffic continues to grow at a “breakneck pace,” with the demands on SerDes speeds increasing accordingly.
The Complexity of High-Speed SerDes
Indeed, high-speed SerDes is an integral part of the networking chain – and a significant speed increase is required to support the bandwidth demands of artificial intelligence (AI), Internet of Things (IoT), and virtual reality (VR) applications. However, SerDes design is a complicated process that typically involves a custom-built analog transistor-level design and a soft/hard custom register transfer level (RTL) for analog control; and in some cases, a microcontroller to enable flexible behavior and in-the-field updates.
“Due to this complexity, a multidisciplinary team of analog, digital, and physical designers and software engineers is required with support from silicon-validation and operations teams,” Sorensen and Moorthi explain. “With the rapidly increasing demands on speed, time to market is imperative for ASIC companies when implementing SerDes in their designs. For this reason, it has become more time and cost effective to source SerDes from an IP vendor specializing in the technology.”
In practical terms, this means ASIC companies must be either deeply knowledgeable in high-speed SerDes integration – or rely on their SerDes IP vendor to support them in their development.
“There are many areas of ASIC development outside of the custom analog/digital placement into ASIC design that require this knowledge, such as substrate design, PCB board design, supply noise, timing analysis and so on,” the two add.
According to Sorensen and Moorthi, the role of the SerDes IP vendor is to ensure the effective integration of its IP into the ASIC. Perhaps not surprisingly, SerDes IP vendors often deal with multiple challenges and issues during the integration process, including pin hookup failure and ensuring accurate design simulation.
IP Pin List
“The IP pin list is defined on the boundary of the IP. It is the role of the ASIC integrator to connect the IP in a manner that ensures correct functionality of the ASIC. If a pin is connected incorrectly, it can often result in a costly silicon re-spin,” the two elaborate. “Generally, correct documentation is enough to ensure the ASIC customer has the relevant knowledge to understand how to connect pins either to controller, registers or custom logic. Additionally, digital simulation should catch most pin hookup issues so long as the models are accurate.”
Looking beyond pin descriptions and models, designers must also consider the many signals that may be on a high-speed clock domain or require synchronization to an external clock domain for proper usage further down the chain. More specifically, the clock domain information for each pin needs to be accurately documented, along with the clock/data/general purpose usage of each pin.
Rambus, says Sorensen and Moorthi, facilitates a thorough review early in the design cycle for customers with design teams to ensure correct pin hookup on the external boundary of the IP.
“The IP design team reviews the physical hookup on the ASIC side to ensure the correct pin usage is fully understood,” the two add. “A list of synchronizer cells used externally to the IP provided by the ASIC integrator enables the IP design team to ensure that clock domain crossings are properly handled.”
When an IP is delivered, simulation models are typically one of first views of interest. As Sorensen and Moorthi point out, this allows engineers to check the interoperability of the IP with the controller and other blocks in the design.
“The IP should be simulated as a standalone design. Reviewing this helps the integrator understand how to hook up the design in the system simulation environment. Further documentation is provided to ensure correct usage of switches and flags in the simulation environment,” the two state. “As a next step, the IP along with the other components should be simulated for the various modes of interest including functional modes, scan modes, and loopback modes. The test plan should include all possible modes of usage of the IP including test and debug modes.”
As Sorensen and Moorthi observe, bring-up lab engineers should have access and familiarity with the testbench and models to help accelerate the bring up process in case a debug situation arises. It is also good practice to run a gate-level simulation once the IP has been routed to rule out timing related violations.
“Rambus enables customers with a simulation review to ensure proper coverage of the functional and test modes prior to tape out,” they add.