ExtremeTech’s Joe Hruska recently analyzed a set of leaked slides that suggest Intel’s plans for its upcoming Xeon cores may “stretch farther into the stratosphere” than originally predicted.
“[The] new data purports to show Intel’s roadmap for 2015 and beyond, stretching all the way to 28 cores and 6 memory channels per CPU,” he explained.
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“The differentiation shown above can be broadly broken down by year, with the introduction of Broadwell-EP in 2015 with up to 22 cores, a Broadwell-EX in 24-core flavor, and finally, Purley, with a Skylake-based CPU and up to 28 CPU cores.”
As Hruska notes, the memory channels also take a jump in this version, with clock speeds up to DDR4-2667.
“It makes sense that Intel would actually bump up the per-CPU memory channels — it keeps the ratio of cores to memory channels roughly similar to the current E7 Xeons, which feature up to 18 CPU cores and have four channels per chip,” said Hruska.
“The net effect of these gains should be most significant in the high-end PC and HPC space. AVX-512 is based-on previous versions of AVX, but isn’t compatible with the 512-bit extensions currently used on Xeon Phi.”
According to Hruska, AVX-512 compatibility in Skylake would imply that Intel widened its registers up to 512-bits for the Xeon flavor of the chip – or fused this capability off in the consumer version of Skylake (if it doesn’t come to market).
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“In theory, this would push Intel CPUs up to 32 FPU instructions per clock per core — 4x what Nehalem offered just 10 years earlier,” he added. “[Of course], actually taking advantage of all that theoretical firepower is more complicated.”
Commenting on the above-mentioned slides, Loren Shalinsky, a Strategic Development Director at Rambus, said that Skylake’s reported capabilities clearly illustrate the continued progression of Moore’s Law.
“The never-ending demand for increased bandwidth and capacity – within a reasonable power envelope – continues unabated. Memory is an essential part of this paradigm, which is why Skylake is primed for DDR4,” he explained.
“DDR4 memory delivers a 40-50 percent increase in bandwidth, along with a 35 percent reduction in power consumption compared to DDR3 memory (currently in servers).”
To get a clear picture of the rise in memory bandwidth to accompany the CPU core rise, says Shalinsky, we need to look at the number of memory channels as well as the bandwidth provided by each channel.
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“In 2010, Nehalem featured 8 cores and 3 memory channels running at 1066Mbits/second. With these purported Skylake features, the maximum core to memory bandwidth ratio has been steadily increasing and is now 43% higher than it was with Nehalem and a modest 10%-15% more than the Broadwell-EX. The bandwidth afforded by DDR4 at speeds of up to 2667 is key to ensuring the memory bandwidth can keep up with the CPUs,” he concluded.
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