The challenges of IP reuse
This entry was posted on Wednesday, September 13th, 2017.
Semiconductor Engineering’s Ed Sperling recently penned an article about the challenges of IP reuse. The basic business proposition for third-party IP, says Sperling, is that it’s cheaper, faster and less problematic to buy rather than build.
[“However], things haven’t exactly worked out according to plan, either for companies that license IP or those that develop it,” he explained.
“For IP licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include multiple builds of dozens of IP blocks, particularly at advanced process nodes.”
IP developers also face their own set of challenges, he emphasizes, as the demand for more customized IP transforms the business from “write-once, use everywhere,” to “write once, modify every time.” Even in cases where the IP is relatively fixed (such as processor cores), says Sperling, customers may require extensive system optimization tweaks.
To further complicate matters, every new rev of a process technology at advanced nodes requires changes to the IP. Designing at 10/7nm is particularly difficult because the process and the IP are in almost constant flux. Nevertheless, even at older nodes the advent of new processes to address new or existing markets have made it more difficult for IP vendors to stay current.
Commenting on the above, Frank Ferro, senior director of product management at Rambus, told Semiconductor Engineering that OEMs once shed ASIC teams in favor of buying commodity IP and chips.
“[This] made it a lot harder for these companies to differentiate themselves. Now companies are hiring back ASIC teams and doing a mixed model,” said Ferro. “They do IP development where it makes sense and add customization. But even with standard IP, they add a little differentiation to make it a little better.”
Nevertheless, says Ferro, the goal is still to build IP and license it to at least 10 customers.
“We’ve been in the custom business because of the nature of hard IP, which means we work with the foundries to develop that IP. But even if it’s off-the-shelf, there are little differences from one design to the next,” he continued. “So even if it’s a stable architecture like 28 [gigabits per second] SerDes, which is a known design, you might only be able to re-use a portion of that because it’s very process-dependent. For 28 SerDes, you have a version to use with PCIe, with PONs (passive optical networks) and with short-reach – and you do that because you don’t want to pay the power and area penalty for re-using the same IP. That happens with automotive IP, too.”
Interested in learning more about the challenges of IP reuse? The full text of “The Limits of IP Reuse” by Ed Sperling can be read here on Semiconductor Engineering.