In simple terms, a root of trust is the security foundation for a system-on-a-chip (SoC) or electronic system. Any functionality that needs to be secure relies in whole or in part on that root of trust. However, the term “root of trust” means different things to different people. In some cases, a root of trust is thought to be a single key that was either provisioned to a device or generated by the device itself. In other cases, a root of trust is seen as code, usually boot code, that is immutable and considered always trusted. A newer definition of a root of trust is a hardware module embedded in a chip or system that provides security functionality that keeps the entire chip or system secure.
Secure Silicon IP Series: Will the Real Root of Trust Please Stand Up? (Part Two)
Rambus Expands Family of CryptoManager Root of Trust Secure Silicon IP Cores
Highlights:
- Offers tailored configurations addressing the security needs of Internet of things (IoT), artificial intelligence (AI), machine learning (ML), cloud, government, military and automotive applications
- Employs fully programmable hardware-level security co-processor with the ability to adapt to a dynamic threat environment
- Purpose-built, complete security solution offers ease of integration into SoC designs
- Features FIPS 140-2 ready crypto module and accelerators and DPA resistant crypto cores; designed for automotive-specific configuration ISO-26262-2018 ASIL-D
SUNNYVALE, Calif. – June 26, 2019 – Rambus Inc. (NASDAQ: RMBS) today announced the expansion of the CryptoManager Root of Trust family of products, a series of fully programmable, hardware-level secure silicon IP cores to address the security needs of applications including IoT, AI, ML, cloud, government, military and automotive. CryptoManager cores employ a siloed architecture. They isolate and secure sensitive code, processes, and algorithms from the main processor cores. This mitigates the risk of critical vulnerabilities like the Meltdown and Spectre security flaws. The CryptoManager Root of Trust is purpose-built for security — it features tailored configurations that allow chip designers to optimize main processors for high performance, while relying on the root of trust to perform security processes.
“Security is a mission critical imperative for SoC designs serving virtually every application space,” said Neeraj Paliwal, vice president of products, cryptography at Rambus. “The Rambus CryptoManager Root of Trust family offers tailored secure silicon IP solutions which chip architects can incorporate to meet the specific security needs of their designs.”
Offering a full array of security services, the CryptoManager Root of Trust enables secure boot and runtime integrity checking, remote authentication and attestation, and hardware acceleration for symmetric and asymmetric cryptographic algorithms. Featuring a layered security model, Federal Information Processing Standards (FIPS) 140-2 certified crypto accelerators, and multiple roots of trust to support independent privilege levels, the CryptoManager Root of Trust serves a wide range of applications.
The CryptoManager Root of Trust creates a foundation for Rambus’ comprehensive CryptoManager suite of solutions, including the CryptoManager Infrastructure for secure provisioning. For more information on the Rambus CryptoManager Root of Trust family of cores, visit rambus.com/security/cryptomanager-platform/root-of-trust/.
CryptoManager Root of Trust Technical Details
Within the product family, seven standard configurations address the specific security requirements and certification standards of different end markets. The RT-730 automotive design offers an ISO-26262-2018 ASIL-D-ready implementation, targeting vehicle-to-vehicle and vehicle-to-infrastructure (V2X), advanced driver-assistance systems (ADAS), and infotainment uses. For cloud, AI and ML accelerator chips, the RT-630 helps secure valuable training models, and training and inference data. For government-focused chip designs, the RT-650 offers a design that targets FIPS 140-2 Cryptographic Module Validation Program (CMVP) certification with Suite B accelerators. The RT-660 extends the functionality of RT-650 with the addition of Differential Power Analysis resistant cryptographic cores.
The CryptoManager Root of Trust family of products offers an end-to-end security implementation, comprised of a fully synthesizable IP core that anchors trust in silicon. It includes state-of-the-art crypto accelerators, security firewalls, an entropy source, secure key generation and derivation, secure one-time programmable (OTP) memory management, and a complete secure embedded firmware stack. The secure firmware stack offers secure boot for the root of trust as well as the SoC CPU(s), communicating securely with the SoC stack and running signed secure applications on the root of trust’s CPU. A reference SDK allows integrators to build secure boot, secure firmware updates and secure applications, with provided examples and references. Available evaluation boards and QEMU allow chip designers to easily evaluate the CryptoManager Root of Trust and secure applications.
Secure Silicon IP Series: Complexity vs. Security (Part One)
This webinar will explore some of the threats facing SoC and processor designers and how can SoCs be architected for both performance and security.
Achronix Chooses Rambus GDDR6 PHY IP for Next-Generation FPGA
Delivering best-in-class solutions for artificial intelligence and hardware acceleration applications
SUNNYVALE, Calif – June 4, 2019 – Rambus Inc. (NASDAQ: RMBS) today announced that Achronix, a leader in FPGA-based hardware data acceleration devices and high-performance eFGPA IP, has selected the Rambus GDDR6 PHY for its next-generation Speedster7t FPGA family. Leveraging the top-end data rates delivered by the Rambus GDDR6 memory interface, the Speedster7t family is optimized for artificial intelligence (AI), machine learning (ML) and high-bandwidth data acceleration applications and workloads.
Designed for performance and power efficiency, the Rambus GDDR6 PHY is beneficial for advanced driver-assistance systems (ADAS), AI, ML, graphics and networking applications. Rambus’ GDDR6 PHY enables the communication to and from high-speed, high-bandwidth GDDR6 SDRAM memory, which is a high-performance memory solution that can be used in a variety of applications that require large amounts of data computation.
“GDDR6 is emerging as a mainstream memory solution for high-performance AI/ML and networking applications, and, in utilizing Rambus’ GDDR6 PHY IP, Achronix is an early leader in adopting the technology to differentiate its next generation of products,” said Hemant Dhulla, vice president and general manager of IP Cores at Rambus. “We are excited to be working with Achronix to expand its portfolio of high-performance FPGA solutions, including its latest Speedster 7t family.”
“New use cases for GDDR6 such as AI/ML require extremely fast data transfer between memory and compute,” said Steve Mensor, vice president of marketing, Achronix. “Rambus’ GDDR6 PHY IP will enable Achronix’ Speedster7t FPGA family to support these high-performance data acceleration applications at a low cost with low latency, allowing it to process complex data loads quickly and efficiently.”
For more information on our latest Rambus GDDR6 high speed memory offerings, please visit www.rambus.com/gddr6. Or, visit Achronix in Booth 861 at the Design Automation Conference (DAC) in Las Vegas, NV from June 2 – 6, 2019 to learn more.
Rambus and Infineon Team Up to Bring Global Smart Card and Mobile Ticketing Offerings to Transport
End-to-end CIPURSE solution to extend worldwide reach, providing flexibility, innovation and security key to future mobility services
SUNNYVALE, Calif. and Glasgow, UK – May 29, 2019 – Rambus Inc. (NASDAQ: RMBS), a technology leader in smart ticketing solutions for public transport, today announced a new strategic collaboration with Infineon Technologies AG, a global leader in semiconductor solutions, to jointly promote smart ticketing solutions for mobile and smart cards that will drive the next generation of mobility services worldwide. Both companies will combine their expertise on the CIPURSE™ open standard for mobile and smart card ticketing to provide end users the most comprehensive choice of solutions for future proof transport ticketing solutions.
CIPURSE™ is an open standard supported by a global community of members of the OSPT Alliance. As key supporters and board members of the OSPT Alliance, Rambus and Infineon recognise the trust and integrity CIPURSE™ provides as a platform upon which to build a flexible and secure interoperable ticketing proposition.
With extensive experience implementing scalable smart mobile ticketing solutions, Rambus will bring its Host Card Emulation (HCE) Ticket Wallet Service and Remote Ticket Download (RTD) solutions to the collaboration, providing secure download and storage of tickets on NFC-enabled smartphones and the ability to deliver tickets remotely to smartcards. Along with Infineon’s CIPURSE™ smart ticketing products, the companies will both be able to better deliver a high level of security for the international smart ticketing market, with mobile and smart card ticketing working in tandem.
Russell McCullagh, vice president and general manager of Rambus Ticketing commented: “Through our collaboration with Infineon, we will be able to increase global trust and awareness of the benefits of this open standards-based approach, which can help make public transport ticketing more accessible for all transport scenarios, whether passengers are on rail, bus or ferry.”
Bernardo Knoblich, head of Transport Ticketing Product Line of Infineon Technologies said: “Our expanded collaboration with Rambus is underlining Infineon’s commitment to open standards-based solutions. Innovative services where smart card-based ticketing is deployed along with mobile solutions on a global scale will improve user convenience and hence drive adoption of new mobility services.”
For more information on the Rambus Smart Ticketing solutions, visit rambus.com/smart-ticketing.
Controllers Newsletter – Q2 2019
Northwest Logic is the HBM2 Controller Market Leader
Since the first demonstration in 2015, Northwest Logic’s HBM2 controllers have become market’s preferred choice:
- 31 customer designs and 9 test chips
- Silicon proven on TSMC, Samsung, Global Foundries processes
- Full support for HBM2, HBM2E and Low Latency HBM devices
- Broadcom, Rambus, eSilicon and Synopsys HBM PHY support
- Used in broad array of AI, data center, networking and HPC applications
“Our HBM Controllers are highly configurable enabling our customers to optimize the performance, size and power of their designs,” said Brian Daellenbach, President of Northwest Logic. For more information please contact Northwest Logic.
eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E) Test Chip with Northwest Logic’s HBM2 Controller Core
eSilicon recently announced the tape out of an 7nm HBM2/HBM2E Test Chip which includes Northwest Logic’s market leading HBM2 Controller. “HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.” “We are pleased to work with our partner, eSilicon, on the validation of our Controller for HBM2E and with the previously taped out low latency test chip,” said Brian Daellenbach, president of Northwest Logic. Click here for more information about eSilicon’s 7nm networking IP platform. Click here for more information on Northwest Logic’s Memory solutions.
Northwest Logic’s PCI Express® 5.0 Solution Available Now
Northwest Logic has been delivering PCI Express solutions for more than a decade. These solutions have been used in many designs including in the military, medical, data storage, communications, broadcast applications in ASICs, structured ASICs and FPGAs. Northwest Logic now adds to this silicon-proven solution its high-performance PCI Express 5.0 Core. The PCI Express 5.0 Solution offers a rich feature-set including:
• High-performance, easy-to-use core with optional scatter-gather DMA support
• PCI Express™ 5.0 specification compliant-backward compatible with PCIe 4/3/2/1
• x16, x8, x4, x2, x1 lane with bifurcation support
• 32 Gbit/s SERDES, RP, EP, Switch support
Contact Northwest Logic for more information and to start your PCIe® 5.0 ASIC designs now!
Automotive Tier1 Advanced Video System Deployed with Northwest Logic’s CSI-2 Controller Cores
German Automotive Tier1s have a long history of delivering products with top quality and reliability including deploying technology targeted at improved automotive safety. “Northwest Logic’s CSI-2 Controller Core solution met all our Video System requirements. After a rigorous evaluation we deployed Northwest Logic’s multi-streaming CSI-2 Controller Receiver (Rx) and Transmitter (TX) Cores in our advanced video system. Their high-quality IP and excellent technical support and high-quality IP enabled our product team to deliver our upcoming multi-stream MIPI video system on time,” said Christian Schwarz, Senior Designer at a German Automotive Tier1. Please contact Northwest Logic for more information.
Northwest Logic Presenting at Rambus China Seminars
Rambus is hosting technical seminars in Shanghai on May 14th and Beijing on May 17th. These seminars will describe how to achieve higher memory and SERDES interface performance and power efficiency in applications such as artificial intelligence and wireline communication. Northwest Logic will be presenting in both the memory and SERDES interface portions of the seminars. For more information and to register click here.
Northwest Logic Will Be Participating In the Samsung Foundry Forum
Northwest Logic, a Samsung HBM Ecosystem Partner (see white paper), will be participating in the Samsung Foundry Forum on May 14, 2019 at the Santa Clara Marriott. Northwest Logic’s controllers are being used by our customers in multiple Samsung Foundry nodes including 8nm”. Please stop by Northwest Logic’s kiosk to learn about Northwest Logic’s HBM2, GDDR6, PCIe 5.0, CSI-2 and DSI-2 controller cores for your next Samsung Foundry design.
Implementing HBM in SIP – a DAC 2019 Session From Samsung Electronics
In this session, Samsung will describe how to implement High Bandwidth Memory (HBM) in System In Package (SiP) applications, including design, verification and test. The presentation reflects more than 3 years of Samsung’s HBM manufacturing proficiency across a wide range of customer applications (HPC, AI, Network, Graphics, etc.). Northwest Logic is an important IP provider in Samsung’s HBM ecosystem. For more details about this session, click here.
Northwest Logic Will Be At Design Automation Conference (DAC) 2019
Northwest Logic will be at DAC 2019 in Las Vegas, June 4th and 5th. Please contact us if you are going to be at DAC and would like to have a face-to-face meeting to discuss our latest Memory, PCIe or MIPI IP products and roadmap.
