This webinar will explore some of the threats facing SoC and processor designers and how can SoCs be architected for both performance and security.
Secure Silicon IP Series: Complexity vs. Security (Part One)
Achronix Chooses Rambus GDDR6 PHY IP for Next-Generation FPGA
Delivering best-in-class solutions for artificial intelligence and hardware acceleration applications
SUNNYVALE, Calif – June 4, 2019 – Rambus Inc. (NASDAQ: RMBS) today announced that Achronix, a leader in FPGA-based hardware data acceleration devices and high-performance eFGPA IP, has selected the Rambus GDDR6 PHY for its next-generation Speedster7t FPGA family. Leveraging the top-end data rates delivered by the Rambus GDDR6 memory interface, the Speedster7t family is optimized for artificial intelligence (AI), machine learning (ML) and high-bandwidth data acceleration applications and workloads.
Designed for performance and power efficiency, the Rambus GDDR6 PHY is beneficial for advanced driver-assistance systems (ADAS), AI, ML, graphics and networking applications. Rambus’ GDDR6 PHY enables the communication to and from high-speed, high-bandwidth GDDR6 SDRAM memory, which is a high-performance memory solution that can be used in a variety of applications that require large amounts of data computation.
“GDDR6 is emerging as a mainstream memory solution for high-performance AI/ML and networking applications, and, in utilizing Rambus’ GDDR6 PHY IP, Achronix is an early leader in adopting the technology to differentiate its next generation of products,” said Hemant Dhulla, vice president and general manager of IP Cores at Rambus. “We are excited to be working with Achronix to expand its portfolio of high-performance FPGA solutions, including its latest Speedster 7t family.”
“New use cases for GDDR6 such as AI/ML require extremely fast data transfer between memory and compute,” said Steve Mensor, vice president of marketing, Achronix. “Rambus’ GDDR6 PHY IP will enable Achronix’ Speedster7t FPGA family to support these high-performance data acceleration applications at a low cost with low latency, allowing it to process complex data loads quickly and efficiently.”
For more information on our latest Rambus GDDR6 high speed memory offerings, please visit www.rambus.com/gddr6. Or, visit Achronix in Booth 861 at the Design Automation Conference (DAC) in Las Vegas, NV from June 2 – 6, 2019 to learn more.
Rambus and Infineon Team Up to Bring Global Smart Card and Mobile Ticketing Offerings to Transport
End-to-end CIPURSE solution to extend worldwide reach, providing flexibility, innovation and security key to future mobility services
SUNNYVALE, Calif. and Glasgow, UK – May 29, 2019 – Rambus Inc. (NASDAQ: RMBS), a technology leader in smart ticketing solutions for public transport, today announced a new strategic collaboration with Infineon Technologies AG, a global leader in semiconductor solutions, to jointly promote smart ticketing solutions for mobile and smart cards that will drive the next generation of mobility services worldwide. Both companies will combine their expertise on the CIPURSE™ open standard for mobile and smart card ticketing to provide end users the most comprehensive choice of solutions for future proof transport ticketing solutions.
CIPURSE™ is an open standard supported by a global community of members of the OSPT Alliance. As key supporters and board members of the OSPT Alliance, Rambus and Infineon recognise the trust and integrity CIPURSE™ provides as a platform upon which to build a flexible and secure interoperable ticketing proposition.
With extensive experience implementing scalable smart mobile ticketing solutions, Rambus will bring its Host Card Emulation (HCE) Ticket Wallet Service and Remote Ticket Download (RTD) solutions to the collaboration, providing secure download and storage of tickets on NFC-enabled smartphones and the ability to deliver tickets remotely to smartcards. Along with Infineon’s CIPURSE™ smart ticketing products, the companies will both be able to better deliver a high level of security for the international smart ticketing market, with mobile and smart card ticketing working in tandem.
Russell McCullagh, vice president and general manager of Rambus Ticketing commented: “Through our collaboration with Infineon, we will be able to increase global trust and awareness of the benefits of this open standards-based approach, which can help make public transport ticketing more accessible for all transport scenarios, whether passengers are on rail, bus or ferry.”
Bernardo Knoblich, head of Transport Ticketing Product Line of Infineon Technologies said: “Our expanded collaboration with Rambus is underlining Infineon’s commitment to open standards-based solutions. Innovative services where smart card-based ticketing is deployed along with mobile solutions on a global scale will improve user convenience and hence drive adoption of new mobility services.”
For more information on the Rambus Smart Ticketing solutions, visit rambus.com/smart-ticketing.
Controllers Newsletter – Q2 2019
Northwest Logic is the HBM2 Controller Market Leader
Since the first demonstration in 2015, Northwest Logic’s HBM2 controllers have become market’s preferred choice:
- 31 customer designs and 9 test chips
- Silicon proven on TSMC, Samsung, Global Foundries processes
- Full support for HBM2, HBM2E and Low Latency HBM devices
- Broadcom, Rambus, eSilicon and Synopsys HBM PHY support
- Used in broad array of AI, data center, networking and HPC applications
“Our HBM Controllers are highly configurable enabling our customers to optimize the performance, size and power of their designs,” said Brian Daellenbach, President of Northwest Logic. For more information please contact Northwest Logic.
eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E) Test Chip with Northwest Logic’s HBM2 Controller Core
eSilicon recently announced the tape out of an 7nm HBM2/HBM2E Test Chip which includes Northwest Logic’s market leading HBM2 Controller. “HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.” “We are pleased to work with our partner, eSilicon, on the validation of our Controller for HBM2E and with the previously taped out low latency test chip,” said Brian Daellenbach, president of Northwest Logic. Click here for more information about eSilicon’s 7nm networking IP platform. Click here for more information on Northwest Logic’s Memory solutions.
Northwest Logic’s PCI Express® 5.0 Solution Available Now
Northwest Logic has been delivering PCI Express solutions for more than a decade. These solutions have been used in many designs including in the military, medical, data storage, communications, broadcast applications in ASICs, structured ASICs and FPGAs. Northwest Logic now adds to this silicon-proven solution its high-performance PCI Express 5.0 Core. The PCI Express 5.0 Solution offers a rich feature-set including:
• High-performance, easy-to-use core with optional scatter-gather DMA support
• PCI Express™ 5.0 specification compliant-backward compatible with PCIe 4/3/2/1
• x16, x8, x4, x2, x1 lane with bifurcation support
• 32 Gbit/s SERDES, RP, EP, Switch support
Contact Northwest Logic for more information and to start your PCIe® 5.0 ASIC designs now!
Automotive Tier1 Advanced Video System Deployed with Northwest Logic’s CSI-2 Controller Cores
German Automotive Tier1s have a long history of delivering products with top quality and reliability including deploying technology targeted at improved automotive safety. “Northwest Logic’s CSI-2 Controller Core solution met all our Video System requirements. After a rigorous evaluation we deployed Northwest Logic’s multi-streaming CSI-2 Controller Receiver (Rx) and Transmitter (TX) Cores in our advanced video system. Their high-quality IP and excellent technical support and high-quality IP enabled our product team to deliver our upcoming multi-stream MIPI video system on time,” said Christian Schwarz, Senior Designer at a German Automotive Tier1. Please contact Northwest Logic for more information.
Northwest Logic Presenting at Rambus China Seminars
Rambus is hosting technical seminars in Shanghai on May 14th and Beijing on May 17th. These seminars will describe how to achieve higher memory and SERDES interface performance and power efficiency in applications such as artificial intelligence and wireline communication. Northwest Logic will be presenting in both the memory and SERDES interface portions of the seminars. For more information and to register click here.
Northwest Logic Will Be Participating In the Samsung Foundry Forum
Northwest Logic, a Samsung HBM Ecosystem Partner (see white paper), will be participating in the Samsung Foundry Forum on May 14, 2019 at the Santa Clara Marriott. Northwest Logic’s controllers are being used by our customers in multiple Samsung Foundry nodes including 8nm”. Please stop by Northwest Logic’s kiosk to learn about Northwest Logic’s HBM2, GDDR6, PCIe 5.0, CSI-2 and DSI-2 controller cores for your next Samsung Foundry design.
Implementing HBM in SIP – a DAC 2019 Session From Samsung Electronics
In this session, Samsung will describe how to implement High Bandwidth Memory (HBM) in System In Package (SiP) applications, including design, verification and test. The presentation reflects more than 3 years of Samsung’s HBM manufacturing proficiency across a wide range of customer applications (HPC, AI, Network, Graphics, etc.). Northwest Logic is an important IP provider in Samsung’s HBM ecosystem. For more details about this session, click here.
Northwest Logic Will Be At Design Automation Conference (DAC) 2019
Northwest Logic will be at DAC 2019 in Las Vegas, June 4th and 5th. Please contact us if you are going to be at DAC and would like to have a face-to-face meeting to discuss our latest Memory, PCIe or MIPI IP products and roadmap.
eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip
Chip facilitates continued support of the latest HBM technologies for eSilicon’s 2.5D FinFET ASICs
SAN JOSE, Calif. — May 9, 2019 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology. The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic. This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.
When compared to HBM2, the HBM2E standard increases total capacity from 8GB to 16GB, bandwidth per pin from 2.4 Gb/s to 3.2 Gb/s and bandwidth per stack from 307.2 GB/s to 410 GB/s. Samsung Electronics announced the industry’s first HBM2E to deliver the 3.2 Gb/s per-pin transfer speed, at NVIDIA’s GPU Technology Conference in March.
Low latency HBM devices have been launched by Renesas Electronics. These devices leverage Renesas low latency memory technology to realize high random-access rate and small data granularity as well as high bandwidth for latency-sensitive applications.
“We are pleased to work with our partner, eSilicon, on the validation of our Controller for HBM2E and low latency applications,” said Brian Daellenbach, president of Northwest Logic. “This validation further strengthens our industry-leading HBM2 Controller solution.”
“HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.”
Read our primer on:
HBM2E Implementation & Selection – The Ultimate Guide »
You can learn more about eSilicon’s 7nm IP platform here, or contact your eSilicon sales representative directly or via [email protected]. You can learn more about Northwest Logic’s HBM2 Controller Cores here.
Contacts:
Sally Slemons
eSilicon Corporation
[email protected]
Nanette Collins
Public Relations for eSilicon
[email protected]
About eSilicon:
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
Collaborate. Differentiate. Win.™
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eSilicon is a registered trademark, and the eSilicon logo, neuASIC and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
Full Disk Encryption of Solid State Drives and Root of Trust
File encryption, file system encryption and full disk encryption (FDE) are methods offered by the industry to allow users to protect their data stored on non-volatile storage devices, such as Solid State Disks (SSD). The main feature of FDE is to protect stored system and user date from unauthorized reading, writing, alteration, moving or rolling back. However, extended security features are key to securing FDE implementation.
