Inventions

Traditional, multi-gigahertz memory interfaces require timing synchronization circuitry in both the controller and memory interface in order to compensate for any skew that arises between clock, data, and command/address (C/A) signals. FlexClocking™ Architecture technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the [...]

In memory architectures, it can be used to deskew data bits inbound to the controller (Reads) in order to compensate for uncertainty in the arrival times of signals. Enhanced FlexPhase™ circuits implemented in a memory controller finely tune the timing relationships between data, command and address (C/A), and clock signals to eliminate the need [...]

As the performance demands of personal and enterprise computing continue to rise, memory system designers are challenged to meet the memory speed and capacity requirements needed to address the growing demand. The traditional method of supporting memory system capacity expansion is through the use of a memory bus with a multi-drop topology, which supports multiple [...]

As CPU speeds continue to increase, memory performance becomes more of a limiting factor in system performance. For system performance to increase, memory performance must increase as well. An important aspect of increasing memory performance is increasing the speed at which data can be transmitted to and from the DRAMs in the memory system. In [...]

As performance requirements and resulting signaling speeds continue to rise, maintaining signal and power integrity in single-ended signaling systems becomes increasingly challenging. Major hurdles include crosstalk, power supply noise, simultaneous switching output (SSO) noise and VREF noise. By employing differential signaling instead of single-ended signaling, designers are able to achieve faster signaling speeds at lower [...]

As memory systems continue to evolve, memory system bandwidth is advancing to higher levels through the use of wider memory system buses and faster per-pin signaling rates. Controller package cost, motherboard routing complexity, and system space constraints make further increases in memory bus widths difficult, and result in an increased emphasis on improving per-pin signaling [...]

In order to meet the extended battery life and performance requirements of future mo-bile devices, memory systems must be able to operate in near-zero power standby states while maintaining very fast wake-up times. Building on the FlexClocking™ archi-tecture, Advanced Power State Management (APSM) features ultra-fast transition times between various power saving and active operating modes [...]

Rambus' 32X Data Rate technology transfers 32-bits of data per I/O on every clock cycle. This enables extremely high bit-transfer rates and per device bandwidth while maintaining relatively low system clock speeds. Use of lower clock speeds reduces system costs and complexity. Reduces power consumption Simplifies design complexity Reduces board and system costs Enables high [...]