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Found 3633 Results
Micro-Threading Technology
https://www.rambus.com/micro-threading-technology/Improvements in DRAM interface throughput have rapidly outpaced comparable improvements in core speeds. Whereas data rates of DRAM interfaces have increased by over an order of magnitude over successive generations, the DRAM core frequency has remained relatively constant. Over time, core prefetch size has increased in order to keep pace with improvements in interface bandwidth. […]
Fully Differential Memory Architecture
https://www.rambus.com/fully-differential-memory-architecture/As data rates continue to increase, signal and power integrity are increasingly difficult to maintain in memory systems with single-ended signaling topologies. To enhance signal integrity and noise immunity across all communications between the memory PHY and the DRAM devices, Rambus implemented a Fully Differential Memory Architecture (FDMA) using a point-to-point topology, for data, clock, […]
Fly-by Command Address
https://www.rambus.com/fly-by-command-address/Conventional, low-speed DRAM systems distribute clock, command, and address signals to multiple DRAMs using a topology in which those signals propagate to all of the DRAMs in the system at approximately the same time. In such systems, the propagation delays on the command and address lines introduce timing skew into the system, thereby limiting the […]
FlexMode™ Interface
https://www.rambus.com/flexmode-interface/As chip design and fabrication costs continue to rise with each new process node, the ability to integrate flexible, cost-effective multi-purpose interfaces becomes increasingly valuable. Traditional multi-modal implementations combine the worst-case signal pin count for the functional blocks of the interface for each memory type growing the pin count, area and cost of the interface […]
FlexLink™ C/A Interface
https://www.rambus.com/flexlink-ca-interface/Traditional industry-standard memory architectures use wide, single-ended command/address (C/A) channels that operate at a considerably lower frequency than the data rate of the system. These wide, multi-drop interfaces require more pins and have greater power requirements. Given the pin and area requirements, scaling of wide busses becomes increasingly impractical. FlexLink™ C/A interface is a full-speed, […]
FlexClocking™ Architecture
https://www.rambus.com/flexclocking-architecture/Traditional, multi-gigahertz memory interfaces require timing synchronization circuitry in both the controller and memory interface in order to compensate for any skew that arises between clock, data, and command/address (C/A) signals. FlexClocking™ Architecture technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the […]
Enhanced FlexPhase™ Timing Adjustments
https://www.rambus.com/enhanced-flexphase-timing-adjustments/In memory architectures, it can be used to deskew data bits inbound to the controller (Reads) in order to compensate for uncertainty in the arrival times of signals. Enhanced FlexPhase™ circuits implemented in a memory controller finely tune the timing relationships between data, command and address (C/A), and clock signals to eliminate the need for […]
Dynamic Point-to-Point
https://www.rambus.com/dynamic-point-to-point/As the performance demands of personal and enterprise computing continue to rise, memory system designers are challenged to meet the memory speed and capacity requirements needed to address the growing demand. The traditional method of supporting memory system capacity expansion is through the use of a memory bus with a multi-drop topology, which supports multiple […]
DLL/PLL on a DRAM
https://www.rambus.com/dllpll-on-a-dram/As CPU speeds continue to increase, memory performance becomes more of a limiting factor in system performance. For system performance to increase, memory performance must increase as well. An important aspect of increasing memory performance is increasing the speed at which data can be transmitted to and from the DRAMs in the memory system. In […]
Differential Rambus Signaling Levels (DRSL)
https://www.rambus.com/differential-rambus-signaling-levels-drsl/As performance requirements and resulting signaling speeds continue to rise, maintaining signal and power integrity in single-ended signaling systems becomes increasingly challenging. Major hurdles include crosstalk, power supply noise, simultaneous switching output (SSO) noise and VREF noise. By employing differential signaling instead of single-ended signaling, designers are able to achieve faster signaling speeds at lower […]
