Rambus announces 56G SerDes PHY on second-gen FinFET process technology

This entry was posted on Wednesday, February 1st, 2017.

Rambus has announced a 56G Multi-protocol SerDes (MPS) PHY developed on second-gen FinFET (Fin Field Effect Transistor) process technology to meet the evolving demands of communications and data center applications.

Doubling DRAM Performance with Conventional Memory

With a scalable ADC-based (analog-to-digital converter) architecture, the 56G SerDes FinFET PHY provides both PAM-4 and NRZ signaling, offering a flexible solution that addresses the needs of long-reach backplane requirements as the industry transitions from 100Gb to 400Gb Ethernet applications.

According to Luc Seraphin, senior vice president and general manager of the Rambus Interface division, the Rambus 56G Multi-protocol SerDes PHY delivers enterprise-class performance across the challenging signaling environments typical of high-speed communication systems.

“To meet the growing demand for high-speed Ethernet, we have developed a scalable new architecture to address the future requirements of higher speeds and increased bandwidth,” he explained. “Developing on FinFET technology allows us to deliver lower power consumption and higher levels of integration levels to support next-generation solutions. This technology also addresses process challenges and is capable of supporting demanding systems with extended product life-cycles.”

It should be noted that Rambus SerDes interfaces are high-quality, complete PHY solutions that are designed with a system-oriented approach to maximize flexibility and facilitate easy integration. They have been optimized for power and area at peak bandwidth, enabling customers to differentiate while maintaining complete compatibility with industry standards.

In addition to 56G, the Rambus SerDes interface family includes:

  • 28G MPS PHY
  • 16G MPS PHY
  • 12G MPS PHY
  • 6G MPS PHY

Interested in learning more? You can check out our SerDes product page here.