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Crypto Accelerator Hardware Cores

Rambus Crypto Accelerator Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software. This allows the CPUs to focus on other important tasks. These superior performance cores are easily integrated into SoCs and FPGAs, and support Suite-B industry standard cryptographic algorithms and random number generators such as AES, 3DES, SHA-2, HMAC, RBG, ChaCha20, and Whirlpool across multiple operating modes. The cores are validated to FIPS 140-2 CAVP.

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Product Brief

How Crypto Accelerator Cores works

The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.

They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP core pass all NIST CAVP vectors. Several of the cores are also available in Differential Power Analysis (DPA) protected versions, extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology. These Crypto accelerator cores are portable to any FPGA or ASIC technologies.

Crypto Accelerator Hardware Cores

The Crypto Accelerator Hardware Cores are provided as RTL reference designs, allowing customers to target their CMOS node or FPGA family of choice. The cores can be integrated into any architecture, e.g. with an appropriate wrapper as bus attachments on an SoC bus, or as part of an inline streaming crypto pipeline. The design data base comprises of a testbench, test vectors, integration data, simulation and synthesis scripts, that can all be adapted easily to match the customer’s preferred design flow and tool chains.

Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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Solution Offerings

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Protecting Electronic Systems from Side-Channel Attacks

Side-channel attacks comprise a wide range of techniques including Differential Power Analysis, Simple Power Analysis, Simple Electromagnetic Analysis, Differential Electromagnetic Analysis, Correlation Power Analysis and Correlation Electromagnetic Analysis. An effective layer of side-channel countermeasures should therefore be implemented via hardware (DPA resistant cores), software (DPA resistant libraries) or both. After layered countermeasures have been implemented, systems should be carefully evaluated to confirm the cessation of sensitive side-channel leakage.

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Inventions

DPA Countermeasures

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DPA Countermeasures are fundamental techniques for protecting against Differential Power Analysis (DPA) and related side-channel attacks. Consisting of a broad range of software, hardware, and protocol techniques, DPA Countermeasures include reducing leakage, introducing amplitude and temporal noise, balancing hardware and software, incorporating randomness, and implementing protocol level countermeasures.

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Aerospace & Defense
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