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Crypto Accelerator Hardware Cores

Rambus Crypto Accelerator Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumption compared to running the same algorithms in software. This allows the CPUs to focus on other important tasks. These superior performance cores are easily integrated into SoCs and FPGAs, and support Suite-B industry standard cryptographic algorithms and random number generators such as AES, 3DES, SHA-2, HMAC, RBG, ChaCha20, and Whirlpool across multiple operating modes. The cores are validated to FIPS 140-2 CAVP.

How Crypto Accelerator Cores works

The Crypto Accelerator Hardware Cores offer chipmakers an easy-to-integrate technology-independent soft-macro security solution, offering various levels of cryptographic acceleration performance.

They are easy to integrate into various SoC and FPGA architectures and development flows, and are all designed to maximize performance versus silicon area requirements. The Rambus IP core pass all NIST CAVP vectors. Several of the cores are also available in Differential Power Analysis (DPA) protected versions, extensively validated using the standardized Test Vector Leakage Assessment (TVLA) methodology. These Crypto accelerator cores are portable to any FPGA or ASIC technologies.

Crypto Accelerator Hardware Core Products diagram

The Crypto Accelerator Hardware Cores are provided as RTL reference designs, allowing customers to target their CMOS node or FPGA family of choice. The cores can be integrated into any architecture, e.g. with an appropriate wrapper as bus attachments on an SoC bus, or as part of an inline streaming crypto pipeline. The design data base comprises of a testbench, test vectors, integration data, simulation and synthesis scripts, that can all be adapted easily to match the customer’s preferred design flow and tool chains.

Solution Offerings

  • Superior performance cryptographic cores optimized for performance, area, and security applications
  • Portfolio of cores for Suite-B algorithms and modes, ChaCha20, and Whirlpool
  • Extensively verified and validated using FIPS140-2 CAVP test vector sets
  • Technology and node independent RTL source code design
  • Synchronous design and interface allows easy integration in various SoC architectures

Configurable Cryptographic Core

  • Verilog RTL reference design
 

Synthesis Inputs

  • SDC constraint file suitable for FPGA or ASIC synthesis
 

Full Documentation

  • Specification documents and Integration guides
 

Functional Testbench

  • NIST-compliant test vectors
CoreCertification Number
AES-AE-16-STDC732
AES-AE-4-STDC731
AES-ECB-16-STDC722
AES-ECB-16-STD-EOC723
AES-ECB-4-STDC720
AES-ECB-4-STD-EOC721
AES-FBC-16-STDC728
AES-FBC-4-STDC727
HMAC_SHA2_224_256_384_512_STDC735
HMAC_SHA2_224_256_STDC736
RBG_CRNG_2_DRBG_AES_16C745
RBG_CRNG_2_DRBG_AES_16C745
RBG_CRNG_2_DRBG_AES_16-variant2C749
RBG_CRNG_2_DRBG_AES_16-variant3C750
RBG_CRNG_2_DRBG_AES_16-variant4C751
RBG_CRNG_2_DRBG_AES_4C744
RBG_CRNG_2_DRBG_AES_4-variant2C746
RBG_CRNG_2_DRBG_AES_4-variant3C747
RBG_CRNG_2_DRBG_AES_4-variant4C748

NIST Website

Introduction to Side-Channel Attacks eBook

Introduction to Side-Channel Attacks

Side-channel attacks conducted against electronic gear are relatively simple and inexpensive to execute. Such attacks include simple power analysis (SPA) and Differential Power Analysis (DPA). As all physical electronic systems routinely leak information, effective side-channel countermeasures should be implemented at the design stage to ensure protection of sensitive keys and data.

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