Rambus has working silicon in its labs for DDR5, the next major interface for DRAM dual in-line memory modules (DIMMs). The register clock drivers and data buffers could help double the throughput of main memory in servers, probably starting in 2019 — and they are already sparking a debate about the future of computing.
Rambus Announces Industry’s First Functional Silicon of Server DIMM Buffer Chipset Targeted for Next-generation DDR5
Provides data center architects early path to next-generation memory speeds
SUNNYVALE, Calif. – Sept. 20, 2017 – Rambus Inc. (NASDAQ: RMBS) today announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype for the next generation DDR5 memory technology. This represents a key milestone for Rambus and the industry’s first silicon-proven memory buffer chip prototype capable of achieving the speeds required for the upcoming DDR5 standard.
“Data-intensive applications like Big Data analytics and machine learning will be key drivers for the adoption of DDR5, with enterprise close behind,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remaining on the leading edge of industry standards.”
According to JEDEC, next-generation DDR5 memory will offer improved performance and power efficiency, providing double the bandwidth and density over DDR4. With that, server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance. This Server DIMM chip prototype leverages the signal integrity and low power, mixed-signal design expertise of Rambus to enable development of next-generation solutions for future data center workloads.
For additional information on our Server DIMM Chipsets, please visit the pages below:
1. Product Solution > DDR5 DIMM Chipset
2. Blog > DDR5 vs DDR4: All the Design Challenges & Advantages
Welcome your new Silicon Valley Chapter President, Jerome Nadel of Rambus!
Get to know your Silicon Valley Chapter President: Jerome Nadel. Jerome is the Chief Marketing Officer at Rambus and has been a CMO Club Member since July 2014. He is active in Chapter Dinners, CMO Club Summits, led CMO roundtable discussions and was a 2016 CMO Awards Finalist. You can connect with Jerome here on Twitter and LinkedIn.
Controllers Newsletter – Q3 2017
Northwest Logic, Rambus and GLOBALFOUNDRIES Demonstrate Complete, Silicon-Proven HBM2 Solution
Northwest Logic, Rambus and GLOBALFOUNDRIES have demonstrated a complete, silicon-proven High Bandwidth Memory Gen2 (HBM2) solution. This solution utilizes the Rambus HBM2 PHY and Northwest Logic’s HBM2 Controller Core on the GLOBALFOUNDRIES 14nm FinFET (FX-14) process. The solution is fully compliant with the JEDEC HBM2 standard supporting data rates up to 2000 Mbps per data pin which enables a total system bandwidth of 256 GB/s. “This high-performance, high-bandwidth and lower-power HBM2 solution from Northwest Logic, Rambus and GLOBALFOUNDRIES is silicon-proven via a test chip. Multiple customer designs are in progress and will be in full production in 2018,” said Brian Daellenbach, President at Northwest Logic. Please visit these links Northwest Logic Controller, Rambus PHY and GLOBALFOUNDRIES for more information.
Northwest Logic’s Expresso DMA Bridge Core Used in Xilinx Accelerator Demos
Northwest Logic’s Expresso DMA Bridge Core is being used in the several Xilinx accelerator demos showcasing – Comp/De-Comp, Erasure Code, SHA1/2-Dedupe, and AES-XTS-128/256. Key features of this IP core include:
- High-throughput, scatter-gather DMA
- High-throughput PCIe-AXI Bridging
- Address translation and security support
- Optimized Root Port bridging support
- Memory-mapped and streaming (FIFO) DMA operation
- Up to 1024 DMA Channels
“Northwest Logic’s high performance Expresso DMA engine plays an important role in accelerator solutions for big data server and storage markets. Xilinx and its ecosystem partners are pleased to work with NWL to integrate their DMA engine in these demonstration platforms,” said Manish Muthal, Xilinx Vice President, Data Center Business. For more information on Northwest Logic, click here.
Mixel and Northwest Logic Close First DSI-2 Design Win
Northwest Logic and Mixel recently closed their first DSI-2 design win using the combination of Mixel’s high-performance, low-power MIPI C/D-PHY and Northwest Logic’s full featured, flexible DSI-2 Controller Core. This DSI-2 solution provides best-in-class performance, features and power consumption. “Mixel is a market leader in MIPI C/D-PHYs and is pleased to see the increasing adoption of MIPI C/D-PHY in both display (DSI-2) and camera (CSI-2) applications,” stated Ashraf Takla, president of Mixel. “Northwest Logic’s DSI-2 and CSI-2 controllers are packaged together with Mixel’s C/D-PHY to provide complete, full-featured DSI-2 and CSI-2 solutions,” added Brian Daellenbach, president of Northwest Logic. Contact Northwest Logic or Mixel for more information. To understand the date rate evolution of C/D-PHY, DSI-2 and CSI-2 see the 2016 MIPI DEVCON Presentation.
Test Evolution Uses Northwest Logic DSI-2 Peripheral Controller Core
Test Evolution’s Intelligent Analyzer (IA) leverages Northwest Logic’s DSI-2 Peripheral Controller Core to provide rapid MIPI DSI-2 with C-PHY protocol validation. The IA acts as a fully compliant DSI-2 Peripheral device to test a SoC Device Under Test (DUT) with a DSI-2 Host interface. The IA provides full C-PHY and DSI-2 command and video test support for complete post silicon validation. “Northwest Logic’s DSI-2 Controller Core enabled us to accelerate our development by using high quality IP with excellent technical support,” said Allen Czamara, VP of Engineering for Test Evolution. Contact Test Evolution or Northwest Logic for more information.
Northwest Logic Adds Fujisoft As A Japan Sales Agent
Northwest Logic has added Fujisoft as a sales agent to support the expanding Japanese market. Fujisoft provides complete solutions including design services, IP cores and boards to its customers. “Northwest Logic, with its set of high-performance PCIe, Memory and MIPI IP cores is an excellent fit for Fujitsoft and its customers,” said Tomomori Ishii, General Manager of the department of Embedded Product solutions of Fujisoft. “We look forward to working with Fujisoft to meet our customer needs in Japan,” said Vinitha Seevaratnam, Product Marketing Engineer of Northwest Logic. For more information, visit Fujisoft’s website.
SiFive’s Chief Executive on Opening a Chip Design Factory
Before he agreed to anything, Naveed Sherwani needed to make 40 phone calls. He had questions about the new RISC-V computer architecture and the company founded by its inventors, SiFive. He had been asked to run it.
Rambus and Northwest Logic Certify Interoperability of HBM2 Interface Solution for High-performance Networking and Data Center Applications
Integrated HBM2 PHY and Memory Controller provide validated, standards-compliant memory subsystem with superior signal integrity and reliability
SUNNYVALE, Calif. – Aug. 23, 2017 – Rambus Inc. (NASDAQ: RMBS), an innovator in semiconductor and IP products, today announced validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The solution builds on the growing ecosystem of Rambus partner products that interoperate with its latest HBM2 PHY IP core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets that require the maximum amount of bandwidth available through HBM2.
“Our work with Northwest Logic gives Rambus the functionality to provide a verified solution that reduces the engineering workload and time to market for chip designers” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “As Rambus extends its footprint in PHY support for leading-edge technologies, collaborative interoperability is essential for our end customers that demand early adoption. Memory interfaces are increasingly important in today’s new workloads, and the combination of Rambus HBM2 and Northwest Logic’ HBM2 Memory Controller core is a natural fit to support customer demands on both sides.”
The Northwest Logic HBM2 Memory Controller Cores are optimized for use in both ASICs and FPGAs, and support full-rate, half-rate and quarter-rate operations. The cores provide a solution that can be configured to exact customer requirements, are silicon-proven and are verified with the Rambus HBM2 PHY.
“Our HBM2 Memory Controller Core has been successfully deployed in a wide variety of customer systems demonstrating high reliability and performance,” said Brian Daellenbach, president of Northwest Logic. “We are excited to offer a complete HBM2 solution with Rambus ensuring our customers achieve the best possible combined memory solution for their high data demands.”
The Rambus HBM2 PHY and Northwest Logic HBM2 Memory Controller are each fully JEDEC compliant to the HBM2 standard, allowing the PHY and memory controller to interoperate. The Rambus HBM2 PHY is a high-performance memory IP core that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed, delivering higher efficiency and lower power consumption compared to other memory solutions on the market. For additional information on Rambus HBM2 PHY solutions, please visit https://www.rambus.com/memory-and-interfaces/ddrn-phys/hbm/
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About Rambus Memory and Interfaces Division
The Rambus Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus products deliver improved time-to-market and first-time-right quality.
About Rambus Inc.
Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile payments, and smart ticketing. At Rambus, we are makers of better. For more information, visit rambus.com.
