Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied on Dennard Scaling and Moore’s Law to ensure the creation of ever more advanced process nodes at a steady cadence.
“However, development costs at each advanced node continue to multiply as Moore’s Law begins to slow and Dennard Scaling fades into the distant past,” he explained.
“Consequently, many in the semiconductor industry are taking a closer look at the advantages of refining the silicon design process at an architectural level, rather than relying primarily on process geometries to solve thorny problems.”
For example, says Ferro, there are a number of distinct physical design challenges associated with architecting higher bandwidth memory and faster PHYs that can no longer be addressed by advanced process nodes alone.
“Indeed, the current generation of DDR4 memory deployed in datacenters runs at 2.4Gbps. The maximum speed grade – 3.2Gbps – is expected to start shipping later this year (2016),” he continued. “Perhaps not surprisingly, achieving a top speed of 3.2Gbps has introduced a number of challenges for both SoC and system designers. More specifically, as memory speeds exceed 2.4Gbps, precise signal integrity analysis of the memory channel is required. This is why there are only a handful of companies with working 3.2Gbps prototype hardware capable of supporting real-world server requirements.”
Over the next five years, says Ferro, server memory will likely demand a 33% increase in bandwidth capability per year to keep pace with processor improvements and avoid serious system bottlenecks. Simply put, DRAM of all variants will have to achieve speeds of over 12Gbps by 2020 for optimal performance.
“Although this figure represents a 4X performance increase over the current DDR4 standard, Rambus Beyond DDR4 silicon has demonstrated that even traditional DRAM signaling still has ample headroom for growth. Such speeds, within reasonable power envelopes, are indeed possible,” Ferro explained. “For example, Rambus’ Beyond DDR4 demo silicon offers a 25% improvement in power efficiency while hitting data transfer rates up to 6.4Gbps in a multi-rank, multi-DIMM configuration. This means the memory interface is three times faster than current DIMMs topping out at 2.133Gbps – and two times the maximum speed specified for DDR4 at 3.2Gbps.”
The 25% power savings, says Ferro, can be attributed to several factors. Firstly, the low-swing signaling reduces the I/O power required on the interface. This design is also ‘asymmetric,’ meaning that complex timing and the equalization circuits are all implemented in the PHY, thus greatly simplifying the DRAM interface and reducing cost. Removing complex timing circuits such as PLLs and DLLs from the DRAM makes it extremely agile, facilitating the rapid entrance and exit from power down mode. Because the memory controller is the originator of all memory requests, it is capable of implementing an aggressive and granular DRAM power management scheme.