DesignCon 2015 kicks off January 27th in Santa Clara, California, where Rambus will be showcasing a wide range of R+ enhanced standard memory and serial IP core solutions.
So be sure to stop by booth #835, where you can learn about multi-modal functionality, low-power signaling modes, per-bit FlexPhase timing adjustment capabilities, enhanced in-PHY testability and wider integration with LabStation™ Validation Platform.
Rambus engineers will also be hosting a full-day training workshop on January 28th, covering various aspects of future system design. More specifically, the session explores industry trends and challenges; signal integrity and architecture considerations for high-speed memory and serial link interface design; as well as advanced memory subsystem implementation, tools and testability.
In addition, Rambus engineers are slated to present the following four papers at the DesignCon Technical Program:
Modeling and Analysis of Differential vs. Single-ended Signaling with Through-Silicon Vias (TSVs) for Low-power/High-speed 3D IC channel design – Outlines the electrical modeling and analysis of differential signaling with TSVs compared to single-ended signaling in terms of various electrical performances such as high-frequency insertion loss, noise coupling and power consumption.
Design and Characterization of Interconnects for Serial Links Operating at 56 Gbps and Beyond – Targets at an intermediate audience and developers of interconnects operating at 6-100 Gbps with some background in classic transmission line theory, basics of signal integrity analysis; signal and systems and some communication theory. The paper describes the methodologies used to design and characterize interconnects: PCB, package, connector, and DC blocking capacitance structures.
Design & Simulation of Equalizer Adaptation Engine in Multi-Protocol Serial Links – Presents a simulation methodology to develop and evaluate the performance of the equalizer adaptation engine for multi-protocol serial links. The paper focuses on techniques to develop a simplified behavioral time-domain model of the adaptation engine, gradually adding more detail, and ultimately correlating the translated RTL code with the original behavioral algorithm.
Design and Characterization of a Low-Power, 6.4 Gbps Data Rate DDR Memory Interface System – Of particular interest to DDR memory system designers, and signal and power integrity engineers, this paper covers challenges, budgeting and characterization of DIMM-based DDR memory interface systems.
Interested in learning more about DesignCon 2015? You can check out our official conference page here.
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