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Home > Press Releases > Interface IP > Controllers

Controllers

Rambus Delivers PCIe 6.0 Controller for Next-Generation Data Centers

Highlights:

  • Pushes performance to 64 GT/s for advanced AI/ML, storage and networking applications
  • Implements full PCIe 6.0 feature set with optimized power, area and latency
  • Offers state-of-the-art data security with integrated IDE engine
Rambus PCIe 6.0 Controller Block Diagram
Rambus PCIe 6.0 Controller Block Diagram

SAN JOSE, Calif. – Jan. 26, 2022 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express® (PCIe®) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.

“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”

Key features of the Rambus PCIe 6.0 Controller include:

  • Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
  • Supports fixed-sized FLITs that enable high-bandwidth efficiency
  • Implements low-latency Forward Error Correction (FEC) for link robustness
  • Internal data path size automatically scales up or down based on max. link speed and width for reduced gate count and optimal throughput
  • Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
  • Supports Endpoint, Root-Port, Dual-Mode and Switch port configurations
  • Integrated IDE optimized for performance

More Information:
For more information on the PCIe 6.0 Controller, please visit our website. Or, view the PCIe 6.0 specification online.

Rambus Delivers CXL 2.0 Controller with Industry-leading Zero-Latency IDE

Highlights:

  • Offers security at speed with integrated IDE modules for unmatched performance in data center infrastructure
  • Provides zero-latency data encryption for CXL.mem and CXL.cache protocols
  • Integrates with Rambus CXL 2.0 PHY for complete CXL interconnect subsystem
CXL 2.0 Controller Block Diagram
Rambus CXL 2.0 Controller with IDE

SAN JOSE, Calif. – Oct. 5, 2021 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced Compute Express Link™ (CXL) 2.0 and PCI Express® (PCIe) 5.0 controllers now available with integrated Integrity and Data Encryption (IDE) modules. Delivering security at speed in CXL is critical to solving the bandwidth bottleneck in data center infrastructure. IDE monitors and protects against physical attacks on CXL and PCIe links. CXL requires extremely low latency to enable load-store memory architectures and cache-coherent links for its targeted use cases. This breakthrough controller with a zero-latency IDE, developed by the engineering team from newly-acquired PLDA, delivers state-of-the-art security and performance at full 32 GT/s speed.

“Successful enablement of CXL use models in data-intensive applications, such as memory sharing between processors and attached AI accelerators, requires security at ultra-low latency,” said Sean Fan, chief operating officer at Rambus. “Delivering controllers with zero-latency security is a testament of our ability to accelerate the development of CXL solutions through the recent acquisition of PLDA, and showcases our unique position to provide integrated interface and security IP solutions.”

The built-in IDE modules, now available in Rambus CXL 2.0 and PCIe 5.0 controllers, employ a 256-bit AES-GCM (Advanced Encryption Standard, Galois/Counter Mode) symmetric-key cryptographic block cipher, helping chip designers and security architects to ensure confidentiality, integrity, and replay protection for traffic that travels over CXL and PCIe links. This secure functionality is especially imperative for data center computing applications including AI/ML and high performance computing (HPC).

Key features include:

  • IDE security with zero latency for CXL.mem and CXL.cache
  • Robust protection from physical security attacks, minimizing the safety, financial, and brand reputation risks of a security breach
  • IDE modules pre-integrated in Rambus CXL 2.0 and PCIe 5.0 controllers reduce implementation risks and speed time-to-market
  • Complete CXL 2.0 and PCIe 5.0 interconnect subsystems when controllers are combined with Rambus CXL 2.0 and PCIe 5.0 PHYs

More Information:

For more information on the Rambus CXL 2.0 and PCIe 5.0 controllers with integrated IDE, please visit our website:

CXL 2.0 Subsystem:

  • CXL 2.0 Controller with IDE
  • CXL 2.0 PHY

PCIe 5.0 Subsystem:

  • PCIe 5.0 Controller with IDE
  • PCIe 5.0 PHY

Rambus Demonstrates Industry-first PCIe® 5.0 Digital Controller IP for FPGAs

Highlights: 

  • Achieves industry-first demonstration of 32 GT/s PCIe 5.0 Digital Controller IP operation on leading FPGA platforms
  • Expands use models for FPGAs by enabling multi-instance, PCIe 5.0 switching and bridging at 32 GT/s speeds
  • Enhances performance and capabilities of FPGAs for use in emulation and prototyping, test and measurement, aerospace and defense, and storage and networking applications

SAN JOSE, Calif. – Aug. 30, 2021 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that Rambus has demonstrated its PCI Express® (PCIe) 5.0 digital controller IP on leading FPGA platforms. PCIe 5.0 performance at 32 GT/s in FPGAs using a soft controller is an industry first, and another demonstration of technical leadership from Rambus. This capability expands the use models of FPGAs by enabling multi-instance, switching and bridging applications and accelerates the performance of FPGAs used in defense, networking, and test and measurement markets.

“We’ve achieved a new industry benchmark with the demonstration our PCIe 5.0 controller operating at 32 GT/s on popular FPGA platforms,” said Scott Houghton, general manager of Interface IP at Rambus. “With the growing importance of FPGAs in markets from defense to the data center, this solution developed by the newly-acquired PLDA team expands the Rambus portfolio and offers the next level of performance for mission-critical applications.”

Features of the Rambus PCIe 5.0 Digital Controller:

  • Verified on leading FPGA platforms
  • Supports up to 32 GT/s data rates
  • Backwards compatible to PCIe 4.0 and 3.1/3.0
  • Supports Endpoint, Root-port, Dual-mode, and Switch-port configurations
  • Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
  • Supports AER, ECRC, ECC, MSI, MSI-X, multi-function, crosslink, DOE, CMA over DOE, and other optional features and ECNs

For more information on the Rambus digital controller, please visit rambus.com/interface-ip/controllers/. Or to find out more details on Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.

Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem

Highlights: 

  • Provides HBM3-ready memory subsystem solution consisting of fully-integrated PHY and digital controller
  • Supports data rates up to 8.4 Gigabits per second (Gbps), enabling terabyte-scale bandwidth accelerators for artificial intelligence/machine learning (AI/ML) and high-performance computing (HPC) applications
  • Leverages market-leading HBM2/2E experience and installed-base to speed implementation of customer designs using next-generation HBM3 memory

HBM3 Ready Memory Subsytem

SAN JOSE, Calif. – Aug. 16, 2021 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the Rambus HBM3-ready memory interface subsystem consisting of a fully-integrated PHY and digital controller. Supporting breakthrough data rates of up to 8.4 Gbps, the solution can deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems. With a market-leading position in HBM2/2E memory interface deployments, Rambus is ideally suited to enable customers’ implementations of accelerators using next-generation HBM3 memory.

“The memory bandwidth requirements of AI/ML training are insatiable with leading-edge training models now surpassing billions of parameters,” said Soo Kyoum Kim, associate vice president, Memory Semiconductors at IDC. “The Rambus HBM3-ready memory subsystem raises the bar for performance enabling state-of-the-art AI/ML and HPC applications.”

Rambus achieves HBM3 operation of up to 8.4 Gbps leveraging over 30 years of high-speed signaling expertise, and a strong history of 2.5D memory system architecture design and enablement. In addition to the fully-integrated HBM3-ready memory subsystem, Rambus provides its customers with interposer and package reference designs to speed their products to market.

“With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs,” said Matt Jones, general manager of Interface IP at Rambus. “Our fully-integrated PHY and digital controller solution builds on our broad installed base of HBM2 customer deployments and is backed by a full suite of support services to ensure first-time right implementations for mission-critical AI/ML designs.”

Benefits of the Rambus HBM3-ready Memory Interface Subsystem:

  • Supports up to 8.4 Gbps data rate delivering bandwidth of 1.075 Terabytes per second (TB/s)
  • Reduces ASIC design complexity and speeds time to market with fully-integrated PHY and digital controller
  • Delivers full bandwidth performance across all data traffic scenarios
  • Supports HBM3 RAS features
  • Includes built-in hardware-level performance activity monitor
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Includes 2.5D package and interposer reference design as part of IP license
  • Features LabStation™ development environment that enables quick system bring-up, characterization and debug
  • Enables the highest performance in applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems

For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.

Rambus Expands High-Performance Memory Subsystem Offerings with HBM2E Solution on Samsung 14/11nm

Highlights: 

  • Supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications
  • Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14/11nm FinFET process
  • Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market

SAN JOSE, Calif. – April 21, 2021 – Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, today announced the Rambus HBM2E memory interface subsystem, consisting of a fully-integrated PHY and controller, is silicon proven on Samsung’s advanced 14/11nm FinFET process. Leveraging over 30 years of signal integrity expertise, the Rambus solution operates up to 3.2 Gbps, delivering 410 GB/s of bandwidth. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

“Our partnership with Rambus brings together industry-leading memory interface design expertise with Samsung’s state-of-the-art process and packaging technologies,” said Jongshin Shin, vice president of Design Platform Development at Samsung Electronics. “Designers of AI and HPC systems can implement platforms using HBM2E memory leveraging Samsung’s advanced 14/11nm process to achieve unmatched levels of performance.”

The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 3.2 Gbps and provides designers with substantial headroom for implementation. Rambus and Samsung teamed to validate the HBM2E PHY and Memory Controller IP in silicon using Samsung’s 14/11nm process and advanced packaging technologies.

“With silicon operation up to 3.2 Gbps, customers can implement HBM2E memory subsystems with the confidence of ample margin for their designs,” said Matt Jones, general manager of IP Cores at Rambus. “Our customers benefit from our comprehensive support that includes 2.5D package and interposer reference designs, helping ensure first-time-right implementations.”

Benefits of the Rambus HBM2E Memory Interface (PHY and Controller):

  • Achieves speed of 3.2 Gbps per pin, delivering a system bandwidth of 410 GB/s from a single HBM2E DRAM 3D device.
  • Fully-integrated and verified in silicon HBM2E PHY and Controller reduces ASIC design complexity and speeds time to market
  • Includes 2.5D package and interposer reference design as part of IP license
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Features LabStation™ development environment that enables quick system bring-up, characterization and debug
  • Supports high-performance applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems

For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.

Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution

Highlights: 

  • Leaders in MIPI® technology join forces to offer a complete display subsystem solution with best-in-class bandwidth efficiency
  • Integrated solution includes PHY, digital controller and VESA Display Stream Compression (DSC) to deliver maximum MIPI DSI-2SM functionality and operational modes
  • Proven, reusable IP solution lowers implementation risk and accelerates time to market
  • Solution enables higher resolutions and frame rates for mobile, AR/VR and automotive display applications

SAN JOSE, CA, and MONTREAL, QC – March 10, 2021 – Mixel, Inc., a leading provider of mixed-signal IPs, Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, and Hardent, Inc., a leading provider of video compression IP cores, announced a state-of-the-art solution for next-generation displays. This integrated solution brings together the IP of the three MIPI® Alliance member companies enabling rapid deployment of mobile, AR/VR and automotive displays leveraging MIPI DSI-2 technology. This optimized solution is available immediately and includes:

  • MIPI C-PHYSM/D-PHYSM Combo from Mixel
  • MIPI DSI-2 Controller from Rambus
  • VESA Display Stream Compression from Hardent

Targeting display applications requiring high bandwidth and excellent power efficiency, this subsystem solution brings a significant improvement in overall throughput available with DSI-2. This level of integration using proven, broadly adopted IP sets a new benchmark for performance, ease of implementation, and time to market.

“We are excited to announce the combined solution with our Mixel MIPI Central partners, Rambus and Hardent, to fill a gap in the MIPI ecosystem,” said Justin Endo, marketing manager at Mixel. “Side-by-side instances of our latest generation of C-PHY/D-PHY combo IP support over 60 Gbps aggregate bandwidth without compression, but with it, we can support up to three times that, enabling state-of-the-art performance, and future-proofing our customers’ designs for years to come.”

“The Rambus fully configurable, high-performance DSI-2 Host and Peripheral Controller cores have been fully integrated, verified and delivered with the Mixel PHY and Hardent DSC, enabling customers to quickly create state-of-the-art display designs,” said Joe Rodriguez, product marketing manager at Rambus.

“We are very pleased to launch this new display IP subsystem with our partners Mixel and Rambus,” says Alain Legault, VP of IP products at Hardent. “Hardent’s DSC IP cores have been fully integrated and verified with the Mixel PHY and Rambus controller IP, giving customers the confidence to leverage the advantages of DSC video compression, all while saving vital time during the design cycle.”

Benefits of the Mixel-Rambus-Hardent MIPI DSI-2 Solution

  • Optimized for ASIC design performance (PPA)
  • Maximized functionality and availability of all MIPI DSI-2 operating modes
  • Lower project risk with a fully integrated and verified IP solution
  • Accelerate ASIC and SoC time to market

Technical Details
Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface MIPI CSI-2® v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification. In C-PHY mode, Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 giga-symbols per second (Gsps) per trio which is an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in the D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18 Gbps in their respective modes.

The Rambus DSI-2 Controller cores are DSI-2 v1.1 compliant and optimized for high performance, low power and small size. The cores are full featured supporting host (Tx) and peripheral (Rx), multiple user interface options, and are highly configurable. 64 and 32-bit core widths are available enabling the user to make clock rate versus size tradeoffs.

Hardent’s VESA Display Stream Compression (DSC) IP cores are designed for use in cutting-edge display applications where visually lossless, ultra-low latency compression is required. DSC video compression increases overall transmission bandwidth on the MIPI DSI-2 transport interface by up to 3X, allowing designers to free up the bandwidth needed to create displays with higher resolutions, faster refresh rates, and greater color depths.

Webinar
For more information about the Mixel, Rambus and Hardent IP subsystem, register now to attend the webinar, “Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus and Hardent” presented by the three companies on April 7th at 11:00am Pacific Time.

Availability
The Mixel, Rambus, and Hardent MIPI DSI-2 / VESA DSC subsystem solution is available today in both host (TX) and peripheral (RX) versions.

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