27% of enterprise IT and business decision makers indicated a supplier’s proven security capabilities are the top factor in their selection criteria, according to IDC’s 2018 Global IoT Decision Maker Survey. And this strong preference for suppliers with a track record of strong security will only increase as the threat environment continues to evolve. There is a growing industry consensus that the path forward requires a philosophy of security by design with the implementation of device security anchored in hardware. Learn how hardware-based security can be harnessed to provide competitive advantage in a world where data is the most valuable commodity.
Pushing the Envelope for AI and ADAS with GDDR6
Building on a strong history as the go-to solution for PC and gaming console graphics, the latest iteration of GDDR is an increasingly attractive solution for leading-edge applications in artificial intelligence (AI) and advanced driver-assistance systems (ADAS). This webinar will outline how the latest technology innovations enable GDDR6 to reach speeds where no memory has gone before, meeting the voracious demand for bandwidth of applications on the frontier of computing.
Rambus Closes Sale of Payments and Ticketing Businesses to Visa
For more information, please visit Visa here.
Divestiture reinforces Rambus’ focus on core strength in semiconductor and accelerated growth in silicon IP and chips
SUNNYVALE, Calif. – Oct. 22, 2019 – Rambus (NASDAQ: RMBS), a premier silicon IP and chip provider dedicated to delivering data faster and safer, today announced the completion of the previously-announced sale of its Payments and Ticketing businesses to Visa (NYSE: V).
“With 30 years of experience pushing the envelope in semiconductor design, we look toward a future of continued innovation to carry on our mission of making data faster and safer,” said Rambus president and CEO Luc Seraphin. “We’re excited to have found an acquirer that will provide the Payments and Ticketing businesses a platform for continued success. Completing this transaction is a critical step forward in refocusing and accelerating the growth of our core semiconductor businesses.”
The sale marks another key milestone in the ongoing execution of Rambus’ strategy, delivering on its core strengths in high-speed interface IP and chips, and embedded security.
SEAKR Selects Rambus SerDes and Security IP for Aerospace and Satellite Communications
Highlights:
- SEAKR chooses Rambus 28G Multi-protocol long reach (LR) SerDes PHY and CryptoManager Root of Trust for aerospace and satellite communications
- Combined SerDes and Security IP portfolio offers a one-stop-shop for chip designers, making data faster and safer
- Silicon-proven technologies help enable faster, more secure, mission-critical aerospace electronic systems
SUNNYVALE, CA, and CENTENNIAL, CO – October 16, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced that SEAKR® Engineering, a leading-edge provider of advanced electronics for space applications, selected the Rambus 28G Multi-protocol LR SerDes PHY and the CryptoManager Root of Trust for its next-generation ASIC and FPGA designs.
“We’re delighted that SEAKR has chosen Rambus high-speed interface and defense-grade security cores to provide their customers innovative and silicon-proven technologies,” said Sean Fan, chief operating officer at Rambus. “Leading-edge IP solutions are mission critical to addressing the system design challenges for aerospace and satellite communications. Rambus best-in-class power, performance and area (PPA), including versatile and multi-protocol SerDes solutions and silicon-proven architecture were key differentiators in SEAKR’s decision.”
Today’s aerospace hardware contains highly-complex microelectronics that include advanced processing, data storage, and data communications capabilities. It is important to deliver both the performance needed by aerospace hardware and the means to ensure the data processed, stored and communicated remains secure. Our industry-leading interface and security IP solutions make possible faster, more secure, mission-critical electronic systems.
The Rambus portfolio of silicon IP provides a one-stop-shop for high-speed interface and security IP. The 28G Multi-protocol LR SerDes PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account to optimize performance and maximize flexibility for today’s most challenging system environments. The CryptoManager Root of Trust is a family of fully-programmable secure co-processors that provides a foundation for system security anchored in hardware and protect against a wide range of attacks with state-of-the-art anti-tamper and security techniques.
“Rambus’ ability to provide IP solutions for both moving and securing data with state-of-the-art performance was a key benefit in the selection process,” said Tony Lowry, ASIC program manager at SEAKR. “We are delighted to partner with Rambus as a valued silicon IP provider for both high-speed interfaces and embedded security, enabling SEAKR to support the advanced performance and data security needs for our aerospace customers, bringing these complex systems to market more quickly.”
For more information on Rambus SerDes PHY offerings, please visit rambus.com/serdes. Find out more details on Rambus security solutions at rambus.com/cryptomanager.
Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
Highlights:
- Provides critical building block to deliver data for next-generation data center, networking, high-performance computing (HPC), artificial intelligence (AI) and machine learning (ML) applications
- Delivers superior power, performance and area (PPA) for extra short reach (XSR) links with innovative architecture designed for leading-edge 7nm process node
- Expands SerDes PHY portfolio for 112G OIF-CEI industry standard
SUNNYVALE, Calif. – Sep. 25, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced the tapeout of its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signaling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections. Rambus continues at the forefront of implementing 112G designs to address the needs for next-generation data-intensive applications.
In today’s increasingly connected world, zettabytes of data are generated constantly by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. AI and ML add new workloads and new data streams from the data center to the edge, driving new architectures to move data. These new architectures, combined with the trend toward chip disaggregation and the industry’s transition to 400Gb and 800Gb Ethernet, will require new, faster interconnect solutions.
“As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances,” said Shane Rau, research vice president, computing semiconductors at IDC. “SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity.”
“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”
Technical Details
The Rambus 112G XSR SerDes PHY will deliver enterprise-class performance within D2D and D2OE interconnects for 400Gb and 800Gb Ethernet environments. To achieve the demanding data rates of these high-speed applications requires an innovative SerDes architectural approach.
The Rambus 112G XSR SerDes PHY includes:
- High-bandwidth connectivity greater than 800 Gbps per millimeter of beachfront making it ideal for D2D and D2OE interconnects in networking and HPC applications
- Designed to provide a low-power, high-speed interface that supports chip disaggregation
- Best-in-class architecture for power, performance, area (PPA) with approximately 1 pJ/bit or 1mW/Gbps power
- Compliance with Optical Internetworking Forum Common Electrical I/O Consortium (OIF-CEI) standard
Availability and Additional Information
The Rambus 112G XSR SerDes PHY is the latest addition to the Rambus leading-edge portfolio of SerDes solutions including the 112G LR SerDes PHY announced earlier this year. The PHY is available for licensing, and early access design customers can engage today. To learn more about Rambus SerDes technology, visit Rambus Booth #408 at the TSMC 2019 Open Innovation Platform® Ecosystem Forum on September 26, 2019 at the Santa Clara Convention Center in Santa Clara, CA.
For more information on various Rambus SerDes PHY offerings, please visit rambus.com/serdes.
Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process
Highlights:
- GDDR6, HBM2, and 112G Long Reach (LR) interfaces designed for TSMC’s industry-leading N7 process technology expand Rambus’ leading-edge memory and SerDes PHY offerings
- Portfolio enables critical building blocks for next-generation data center, networking, wireless 5G, high-performance computing (HPC), advanced driver assistance systems (ADAS), artificial intelligence (AI) and machine learning (ML) applications
SUNNYVALE, Calif. and SANTA CLARA, Calif. – Sep. 23, 2019 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology. Leveraging almost 30 years of high-speed interface design expertise and using leading process technology, Rambus offers GDDR6, HBM2 and 112G LR PHY IP available for licensing. These solutions enable demanding applications for data center, networking, wireless 5G, HPC, ADAS, AI and ML.
As the fastest discrete memory interface from Rambus, GDDR6 memory PHY adds to TSMC’s most comprehensive portfolio of silicon-proven intellectual property (IP), design tools and Reference Flows through the TSMC IP Alliance Program, a key component of TSMC Open Innovation Platform® (OIP). Along with HBM2 and 112G LR SerDes PHY, Rambus offers leading-edge memory and serial link interfaces for a broad range of high-performance applications.
“TSMC OIP Alliance partners continue to deliver innovative solutions that will address the tremendous demands for computing power driven by AI and next-generation networks,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “We’re pleased with the availability of Rambus’ high-speed memory and SerDes interface solutions on TSMC’s industry-leading N7 process technology to address customer’s requirements for the most demanding applications.”
Expanding beyond the traditional GPU and graphics applications, GDDR6 and HBM2 address market needs in multiple, advanced applications like AI/ML, ADAS and networking, as memory bandwidth becomes more critical for overall system performance. As the industry rapidly transitions to 400 and 800GbE communications systems, 112G LR is a key building block necessary to support the ever-growing demand for more bandwidth in data center and network applications.
“This announcement highlights Rambus’ leadership in high-speed SerDes and memory PHY IP, leveraging the company’s long tradition of signal- and power-integrity expertise,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are very proud to be able to offer these advanced solutions as part of the TSMC ecosystem.”
Availability
The Rambus GDDR6 and HBM2 Memory PHYs, and 112G LR SerDes PHY are available from Rambus today for licensing and integrating into system-on-chip (SoC) designs.
Demonstration Details at TSMC 2019 Open Innovation Platform® Ecosystem Forum
Join Rambus in Booth #408 at the TSMC 2019 Open Innovation Platform® Ecosystem Forum on September 26, 2019 at the Santa Clara Convention Center in Santa Clara, California and learn more about its extensive portfolio of interface IP and innovation in advanced memory and interface technology.
Additional Information
To learn more about the TSMC 2019 Open Innovation Platform® Ecosystem Forum, visit https://www.rambus.com/event/tsmc-oip-santa-clara-2019/. For additional details about Rambus silicon applications or more information on our latest Rambus high-speed memory and SerDes PHY solutions, go to rambus.com/interface-ip/.
