Optimizing data centers with DDR4 buffer chips
This entry was posted on Wednesday, December 21st, 2016.
DDR4 memory delivers up to 1.5x performance improvement over DDR3, running at 2.4Gbps- 3.2 Gbps, while reducing power by 25% on the memory interface. However, the shift to higher speeds degrades electrical signal integrity, especially when multiple modules are added to a system. Consequently, achieving higher capacities at more advanced speeds has become quite challenging.
To overcome these limitations, specialized clocks and dedicated DDR4 memory buffer chips have been integrated onto DIMMs. Put simply, buffer chips allow server designers to maintain high-speeds with DDR4, while enabling the higher capacity demanded by Big Data applications. More specifically, multiple loads (DRAM devices) tend to reduce the maximum speed which the bus can reach.
Buffer chips help improve system signal integrity by reconditioning the signal coming from the CPU and forwarding it to DRAM, thereby enabling higher operating data rates. In addition, buffer chips facilitate optimized RAS (row address strobe), with the silicon verifying correctness of commands and data.
As expected, DDR4 buffer chips offer several distinct advantages over the previous generation (DDR3), including faster speeds, higher usable bandwidth, larger device density and more banks (16). In addition, DDR4 defines CID for up to 8 high stack addressing, with smaller DDR4 row sizes (x4 devices) lowering power sipping and improving performance for multi-threaded applications.
Moreover, DDR4 buffer chips offer lower voltage consumption at 1.2v, uses (POD) VDDQ termination, reduces I/O current draw and eliminates the need for a voltage pump with VPP. In terms of specific RAS improvements, DDR4 buffer chips support register parity checks and command blocks, optional CRC usage for high data rates, boundary scans (connectivity test mode), MRS readout via MPR and native ECC support for DDR4 SoDIMM.
Clearly, increased memory capacity and performance are critical for data centers tasked with solving today’s complex problems with the storage and analysis of huge data sets. This is precisely why our DDR4 Data Buffer (DB) — iDDR4DB2-GS02 — enables DDR4 Load Reduced Dual Inline Memory Modules (LRDIMMs) to deliver high-bandwidth performance (when combined with our DDR4 RCD) with twice the capacity of DDR4 Registered DIMMs (RDIMMs).
Designed to meet the demanding requirements for real-time, memory-intensive applications, the DB delivers enhanced performance and margin at 2400 Mbps with built-in support for future data rates up to 2666 Mbps. This facilitates the highest speeds and robust operation when multiple LRDIMMs populate the memory channel for the highest system capacities.
The iDDR4DB2-GS02 dual 4-bit bidirectional data register with differential strobes is designed for 1.2 V VDD operation. The device has a dual 4-bit host bus interface connected to a memory controller and a dual 4-bit DRAM interface that is connected to two x4 DRAMs. It also has an input-only control bus interface that is connected to a DDR4 Register. This interface consists of a 4-bit control bus, two dedicated control signals, a voltage reference input and a differential clock input.
All DQS inputs are pseudo-differential with an internal voltage reference, while all DQ outputs are VDD terminated drivers optimized to drive single or dual terminated traces in DDR4 LRDIMM applications. The differential DQS strobes are used to sample the DQ inputs and are regenerated in the DDR4 DB for driving out the DQ outputs on the opposite side of the device. The iDDR4DB2-GS02 also supports dedicated pins for ZQ calibration and for parity error alerts.
Interested in learning more? You can check out our server DIMM chipsets product page here.