Facing a growing matrix of threats, semiconductors must be designed with security as a fundamental consideration. In this webinar, Rambus VP and General Manager for Rambus Security, Neeraj Paliwal, discusses the principles and methodologies for secure chip design and provisioning.
Security for Design Approach for Semiconductors
Data Center Evolution
Ed Sperling, Editor in Chief of Semiconductor Engineering moderates a far-ranging roundtable on the future of data center development. IDC research vice president, Shane Rau, discusses the macro trends and their impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level.
Choosing the Right Root of Trust
A hardware root of trust (RoT) provides the secure foundation for a chip or electronic system. A broad range of RoT solutions are available for implementation. In this webinar, Rambus security expert, Bart Stevens, will discuss the considerations for selecting the right root of trust for a target application.
Protecting Data in Motion with MACsec
Providing Layer 2 security, MACsec is becoming the predominant solution for safeguarding network traffic. In this webinar, Rambus security expert, Gijs Willemse, will discuss the design and implementation of hardware-based MACsec security. The Rambus MACsec protocol engines with performance to 800G will be covered.
PCI Express Selection and Implementation
The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Phani Paladugu and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. The silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller is covered.
HBM2E Selection and Implementation
HBM2E DRAM is the latest generation of high bandwidth memory enabling the most advanced AI accelerators and HPC solutions. In this webinar, Rambus technology experts Frank Ferro and Joe Rodriguez discuss the selection and implementation considerations for HBM2E memory solutions. The silicon-proven Rambus interface solution consisting of integrated PHY and memory controller is covered.
