MIPI DSI-2 Controller Core
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The Rambus MIPI DSI-2 controller core is optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management. An ASIL-B version of the core is available and includes a Safety Manual, Design Failure Mode & Effects Analysis (DFMEA) and Failure Mode, Effects and Diagnostic Analysis (FMEDA).
Leveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays
Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.
Solution Offerings
- Fully MIPI DSI-2/DSI standard compliant
- 32 and 64-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 9.0+ Gbps D-PHY data lanes
- Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
- Supports all data types
- Easy-to-use native interface
- Optional video interface
- Enhanced features available: VHM, ARP, EVFP, VRR
- Delivered fully integrated and verified with target MIPI PHY
- Optional ASIL-B Ready safety deliverables
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Engineering Design Services:
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| DSI-2/DSI | 9.0+ | Mobile, IoT, Automotive |







