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Rambus Partner Program

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Ecosystem Partners

Rambus Partner Program

Rambus collaborates with industry-leading companies to create an ecosystem that provides total solutions for our customers. Ecosystem partners include semiconductor foundries, physical (PHY) IP developers, microprocessor IP vendors, FPGA suppliers, EDA tools and validation labs, ASIC and SoC designers, and DPA solution providers.

Semiconductor Foundries

Most Rambus IP solutions are process and foundry independent, but Rambus works closely with leading semiconductor foundries to ensure compatibility and to provide solutions incorporating the latest technology developments.

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Physical (PHY) IP Developers

Rambus works with PHY/SerDes IP vendors to provide complete IO and Memory subsystems to our customers. Our trusted ecosystems partners include:

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Microprocessor IP Vendors

As a leading provider of high-performance interface and security IP, Rambus works closely with leading microprocessor IP vendors to ensure quality solutions and fast time-to-market for customers.

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FPGA Suppliers

Rambus provides IP solutions tailored to FPGA implementations in collaboration with industry-leading FPGA suppliers.

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EDA Tools and Validation Labs

Rambus works closely with leading suppliers of VIP test suites and validation labs to ensure the highest quality of our IP deliverables.
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ASIC and SoC Designers

Rambus works closely with industry-leading ASIC and SoC designers to incorporate Rambus state-of-the-art IP into customer products.

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Security Solutions Developers

Developers create cores, software libraries, and DPA resistance analysis tool solutions incorporating our patented DPA countermeasures. Partnerships enable preferred access to Rambus DPA licensees and close engagement with world-class cryptography engineers at Rambus.

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Security

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Explore innovations that enable the superior performance of Rambus solutions

DPA Countermeasures Fundamental techniques to protect against side-channel attacks including a broad range of hardware, software and protocol techniques to secure tamper resistant devices

Inventions

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Inventions

Explore innovations that enable the superior performance of Rambus solutions
32X Data Rate Transfers 32 bits of data per I/O on each clock cycle – 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus
Advanced Power State Management Advanced power states in a memory system that enable and disable critical circuitry, such as input receivers and clock circuits, provide an effective way to lower memory system power for various system performance levels.
Asymmetric Equalization Enables very high bandwidth on next generation memory systems. Signal equalization is applied asymmetrically across the memory PHY and DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device.
Binary Pixel Binary pixel enables image sensors to sense photons using discrete thresholds, similar to the human eye, for better sensitivity across the gamut of dark to bright and improved dynamic range.
Buffered Modules As memory systems continue to evolve, memory system bandwidth is advancing to higher levels through the use of wider memory system buses and faster per-pin signaling rates.
Channel Equalization Improves receive eye and system margins by reducing Inter-Symbol Interference (ISI) in high speed parallel and serial link channels.
Clock Multiplying DLL Improves integration levels and noise rejection capability for high speed parallel and serial links.
Clocked DDR Address/Control Sending address and control information with a double data-rate signals improves memory performance efficiency and enables higher effective bandwidth.
Color Temperature Change Cost-effectively enables in-lamp color temperature change from warm to neutral to cool with the turn of a dial through the use of an adjustable remote phosphor and a color mixing light guide.
Core Prefetch Improves interface bandwidth while allowing the core to operate at a lower frequency.
Differential Rambus Signaling Levels (DRSL) A low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO™ cell to XDR™ DRAM devices.
Digital CDR with Fast Recovery Enables fast recovery with low-latency from a low-power state.
DLL/PLL on a DRAM Improves maximum operating frequency of a memory system by optimizing Input/Output (IO) timing.
Double Bus Rate Technology Doubles the transfer rate out of a memory core without the need for higher system clock speeds.
DPA Countermeasures Fundamental techniques to protect against side-channel attacks including a broad range of hardware, software and protocol techniques to secure tamper resistant devices
Dual Loop PLL/DLL Reduces power, silicon area, and cost of an integrated circuit using a PLL/DLL. Allows a PLL/DLL to lock to several arbitrary phases while sharing critical common circuitry.
Dynamic Point-to-Point Enables memory upgrades and expandable capacity while maintaining high-performance point-to-point signaling.
Dynamic Point-to-Point Technology Enhanced Enables the performance, scalability and capacity needs of next generation memory systems. DPP supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity.
Enhanced FlexPhase™ Timing Adjustments Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with command/address and clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase circuits for very high performance memory systems operating at data rates of up to 20Gbps. Enhanced FlexPhase technology was developed through the Rambus Terabyte Bandwidth Initiative.
FlexClocking™ Architecture FlexClocking technology is an architecture that utilizes asymmetric partitioning and places critical calibration and timing circuitry in the controller interface, greatly simplifying the design of the DRAM interface.
FlexLink™ C/A Interface Industry’s first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
FlexMode™ Interface Enables support of differential and single-ended memory interfaces in a single SoC package design, with no additional pins, through programmable assignment of signaling IOs as either data or command/address.
FlexPhase™ Timing Adjustment Circuits Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip-to-chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology’s automatic centering of data and clock offers designers a quick and easy design solution for high-speed chip interconnections.
Fly-by Command Address Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates.
Fully Differential Memory Architecture Industry’s first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. Fully Differential Memory Architecture (FDMA) enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
Jitter Reduction Technology Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems.
Lensless Smart Sensor Low-power, low-cost visual sensing technology that captures information-rich scene data in a tiny form factor using a revolutionary new approach to optical sensing.
Micro-Threading Technology Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
MicroLens® Optics Light distribution features that provide customizable control of uniformity and ray angle for superior application efficiency.
Module Connector Compensation Improves operating frequency of systems utilizing module connectors by mitigating the impedance discontinuity of the electrical interconnection.
Module Impedance Compensation Improves operating frequency of a module by mitigating the discontinuity caused by soldered-on device loading.
Module Threading Module Threading improves the throughput and power efficiency of a memory module by applying parallelism to module data accesses.
Multi-Level Signaling Applied to Backplanes Improves data rates and systems margins in high-speed parallel and serial links used in frequency limited channels.
Near Ground Signaling Near Ground Signaling (NGS) is a single-ended, ground-terminated signaling technology that enables high data rates at significantly reduced IO signaling power and design complexity, while maintaining excellent signal integrity.
On Die Termination Calibration Incorporates On Die Termination impedance improving the signaling environment by reducing the electrical discontinuities introduced with off-die termination.
Output Driver Calibration Improves data rates and system voltage margin by maintaining stable current or voltage drive levels referenced to a precision external resistor.
Phase Interpolator-Based CDR Reduces cost, power, and area of a clock and data recovery circuit, and improves jitter performance in high-speed parallel and serial links versus PLL clock and data recovery (CDRs).
SolidCore™ Reflectors Compact reflectors capable of producing tightly controlled, efficient and high-intensity beams ideal for spotlights.
Spatial Oversampling Spatial oversampling sub-divides Individual pixels to capture more data and extend dynamic range of the imager.
System Flight Time Levelization Enables very large capacity bussed memory or logic systems which operate at high frequency. Simplifies read/write scheduling from the controller logic.
Temperature Compensated Self-Refresh Enables lower memory power during self-refresh by compensating the refresh rate based on temperature.
TruEdge™ LED Coupling LED-to-light guide coupling technology that delivers 93 to 96 % of total LED output to the light guide.
Variable Temporal Oversampling Variable temporal oversampling takes multiple samples during a single exposure period to avoid pixel saturation improving the sensor’s signal-to-noise ratio and low-light performance for better indoor and nighttime photography.
Very Low-Swing Differential Signaling Very Low-Swing Differential Signaling (VLSD) is a bi-directional, ground-referenced, differential signaling technology which offers a high-performance, low-power, and cost-effective solution for applications requiring extraordinary bandwidth and superior power efficiency.
VirtuOptic™ Reflectors Produce a highly collimated, highly efficient light output while delivering precise ray angle control.
Wide Frequency Range PLL Simplifies parallel and serial link applications with continuous, wide-range frequency adjustment capability.

Securing ultra-low-power devices

Ernest Worthman of Semiconductor Engineering recently noted that future ultra-low-power (ULP) IoT devices require a new paradigm for handling cryptography.

“To optimize the power in a ULP device, cryptography and otherwise, there are two approaches that can be uses; steady-state low-power over time and pulsed operation over time,” he explained. “[However], the main issue surrounding cryptography in ULP devices is the relationship between functionality and power utilization.”

Building a secure foundation for wearables

As Worthman points out, traditional cryptographic algorithms are power- and clock-cycle hungry. Essentially, they are the exact opposite of the IoE devices: computationally intensive.

“That is their job – to check everything that can be compromised and that takes power,” he continued. “ULP devices, being computationally constrained, need to make every clock cycle and micro amp count. The two are not mutually compatible.”

According to Worthman, there are a number of approaches to maximizing the limited resources in ULP devices, without foregoing adequate cryptography functionality. For example, the industry could develop smarter decision-making circuitry capable of deciding what needs to run under a cryptographic envelope. Another option would be the coding of lighter weight algorithms and ciphers.

However, as NXP product marketing manager Gordon Cooper told Semiconductor Engineering, the industry cannot simply go to lower power and architecture.

“You have to maintain performance,” he emphasized. “As we go down in process architecture you have that performance for less power, but now you have leakage issues.”

Simon Blake-Wilson, VP of products and marketing at Rambus‘ Cryptography Research Division, points out that leakage often goes along with integration issues. Indeed, at the most advanced nodes, be it security, processor or I/O block with security built in, all need to fit into the surrounding components of a device.

“If you make something that is trivial to integrate with, it will make a huge difference,” said Blake-Wilson. “It’s a good tradeoff of achievable targets, trying to address ease of use for the designers, for the managers of the devices.”

According to Steven Woo, VP of enterprise solutions technology at Rambus, power-related semiconductor security concerns may prompt a general reassessment of how future chips and electronics are designed.

“Security requires power to operate, but the flip side is that power is noisy. When you activate circuits you can monitor that noise,” he told Semiconductor Engineering back in July. “There’s a growing problem with differential power analysis. What it really comes down to is that you’re trying to give confidence for some period of time, so now you have to determine what is a useful lifetime and how long you’re going to guard it.”

As we’ve previously discussed on Rambus Press, physical electronic systems routinely leak information about the internal process of computing. In practical terms, this means attackers can exploit various side-channel techniques to gather data and extract secret cryptographic keys.

As such, the Rambus Cryptography Research division has designed a range of DPA countermeasures that offer a combination of software, hardware and protocol techniques specifically designed to protect tamper-resistant devices from side-channel attacks. These include leak reduction, incorporating randomness, generating amplitude and temporal noise, as well as executing protocol-level countermeasures.

Interested in learning more about how Rambus is helping to secure SoCs, devices and content? You can read more about our DPA countermeasures here, CryptoFireWall Cores here and CryptoManager platform here.

Cracking SIM cards with side-channel attacks

A Jiao Tong University researcher has exploited side-channel attack techniques to crack the encryption codes protecting 3G and 4G cards.

“[The cards use] AES-128, which is supposed to be virtually unbeatable by a brute-force attack, but turns out to be easy to defeat using side-channel analysis,” explained Iain Thomson of The Register. “Side-channel attacks measure things like power consumption, electromagnetic emissions and heat generation to work out what is going on in a chip. The technique has been around for years, and requires physical access to the target device.”

internetbandaid

Have you read our primer?
– Side-channel attacks: explained

As Thomson reports, Yu Yu and his university team tracked power levels using an oscilloscope, monitored data traffic with an MP300-SC2 protocol analyzer and correlated the results with a SIM card reader and a standard PC.

“With this simple setup they cracked eight commercial SIM cards in between 10 and 80 minutes,” said Thomson. “Yu [also] demonstrated how the cloned SIM card can successfully impersonate the owner in class [and] showed how a cloned card could change the password on an Alipay and potentially drain the account.”

According to Yu, the above-mentioned hack is based on known differential power analysis attacks.

“The move to AES-based encryption algorithms in 3G/4G USIM cards did not systematically take advantage of state-of-the-art countermeasures against side-channel attacks,” he added. “Indeed, the USIM cards we analyzed essentially relied on plain (unprotected) software implementations of the AES.”

Helena Handschuh, a Director at Rambus’ Cryptography Research division, co-designed the MILENAGE standard discussed in Yu’s Black Hat paper. According to Handschuh, AES-128/Rijndael was chosen for MILENAGE in 2001 so that side-channel countermeasures could be easily incorporated in a SIM-class platform.

“Yu Yu’s paper demonstrates once again that, even though these algorithms are mathematically strong and unbroken, all implementers of crypto need to be aware of side-channel attacks and take appropriate steps to mitigate them,” Handschuh concluded.

As we’ve previously discussed on Rambus Press, physical electronic systems routinely leak information about the internal process of computing. In practical terms, this means attackers can exploit various side-channel techniques to gather data and extract secret cryptographic keys.

As such, the Rambus Cryptography Research division has designed a range of DPA countermeasures that offer a combination of software, hardware and protocol techniques specifically designed to protect tamper-resistant devices from side-channel attacks. These include leak reduction, incorporating randomness, generating amplitude and temporal noise, as well as executing protocol-level countermeasures.

Interested in learning more about how Rambus is helping to secure SoCs, devices and content? You can read more about our DPA countermeasures here, CryptoFireWall Cores here and CryptoManager platform here.

When power becomes a problem

Semiconductor Engineering editor in chief Ed Sperling recently reported that the current emphasis on lowering power – in everything from wearable electronics to data centers – is turning into a “perfect storm” for the semiconductor ecosystem.

“In the past, most issues involving power—notably current leakage, physical effects such as electromigration, electrostatic discharge, RC delay and reduced battery life from inefficient designs—were dealt with by large, sophisticated engineering teams at leading-edge process nodes,” Sperling explained.

securing-the-iot-starts-at-the-core

“When they couldn’t solve those problems the foundries stepped in and adjusted their processes. But with 55nm now considered a mainstream process for the Internet of Things, and most designs now using multiple cores and power domains—sometimes as many as 100 power domains per design—everyone is being forced to grapple with incredibly complex power techniques.”

To make matters worse, says Sperling, the manufacturing side is already dealing with its own power-related problems, which includes shrinking gate oxides between ever-thinner wires, increasing dynamic power density at 16/14nm and beyond, as well as a massive industry effort to create next-generation processes capable of handling increasingly complex designs.

According to Steven Woo, VP of enterprise solutions technology at Rambus, one particular issue that continues to grow in importance is power integrity.

“A good analogy is what happens if you turn on all the water inside a building,” Woo told Semiconductor Engineering. “You lose pressure everywhere. For a chip, if you turn on every subsystems, that’s devastating. You may not have enough voltage to turn on everything, and power integrity goes down.”

Not surprisingly, power-related security concerns may also prompt a reassessment of how future chips and electronics are designed.

“Security requires power to operate, but the flip side is that power is noisy. When you activate circuits you can monitor that noise,” he added. “There’s a growing problem with differential power analysis. What it really comes down to is that you’re trying to give confidence for some period of time, so now you have to determine what is a useful lifetime and how long you’re going to guard it.”

As we’ve previously discussed on Rambus Press, physical electronic systems routinely leak information about the internal process of computing. In practical terms, this means attackers can exploit various side-channel techniques to gather data and extract secret cryptographic keys.

As such, the Rambus Cryptography Research division has designed a range of DPA countermeasures that offer a combination of software, hardware and protocol techniques specifically designed to protect tamper-resistant devices from side-channel attacks. These include leak reduction, incorporating randomness, generating amplitude and temporal noise, as well as executing protocol-level countermeasures.

Interested in learning more about how Rambus is helping to secure SoCs, devices and content? You can read more about our DPA countermeasures here, CryptoFireWall Cores here and CryptoManager platform here.

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